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PRELIMINARY DATA SHEET
MICRONAS
MSP 3400D, MSP 3410D Multistandard Sound Processors
Edition May 14, 1999 6251-482-2PD
MICRONAS
MSP 34x0D
Contents Page 5 5 5 6 6 6 6 7 7 7 10 10 10 11 11 12 12 12 12 12 12 12 13 13 13 13 13 15 15 15 16 17 18 19 19 19 19 19 20 Section 1. 1.1. 1.2. 2. 2.1. 2.2. 2.3. 3. 3.1. 3.2. 4. 4.1. 4.1.1. 4.1.2. 4.1.3. 4.1.4. 4.1.5. 4.1.6. 4.1.7. 4.1.8. 4.1.9. 4.1.10. 4.2. 4.2.1. 4.2.2. 4.3. 4.3.1. 4.4. 4.5. 4.6. 4.7. 5. 5.1. 5.2. 5.2.1. 5.2.2. 5.2.3. 5.2.4. 5.3. Title Introduction Common Features of MSP 34x0D Specific Features of MSP 3410D Basic Features of the MSP 34x0D Demodulator and NICAM Decoder Section DSP Section (Audio Baseband Processing) Analog Section Application Fields of the MSP 34x0D NICAM plus FM/AM-Mono German 2-Carrier System (Dual-FM System) Architecture of the MSP 34x0D Demodulator and NICAM Decoder Section Analog Sound IF - Input Section Quadrature Mixers Low-pass Filtering Block for Mixed Sound IF Signals Phase and AM Discrimination Differentiators Low-pass Filter Block for Demodulated Signals High-Deviation FM Mode FM Carrier Mute Function in the Dual-Carrier FM Mode DQPSK Decoder NICAM Decoder Analog Section SCART Switching Facilities Stand-by Mode DSP Section (Audio Baseband Processing) Dual-Carrier FM Stereo/Bilingual Detection Audio PLL and Crystal Specifications ADR Bus Interface Digital Control Output Pins I2S Bus Interface I2C Bus Interface: Device and Subaddresses Protocol Description Proposal for MSP 34x0D I2C Telegrams Symbols Write Telegrams Read Telegrams Examples Start-Up Sequence: Power-Up and I2C-Controlling
PRELIMINARY DATA SHEET
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Contents, continued Page 21 21 22 22 23 23 24 25 25 27 28 30 31 32 32 32 32 33 33 33 33 33 33 35 35 35 35 35 35 37 37 39 40 40 41 41 42 42 43 44 44 45 45 46 46 46 Section 6. 6.1. 6.2. 6.3. 6.4. 6.4.1. 6.4.2. 6.5. 6.5.1. 6.5.2. 6.5.3. 6.5.4. 6.6. 6.6.1. 6.6.2. 6.6.3. 6.6.4. 6.6.5. 6.6.6. 6.6.7. 6.6.8. 6.6.9. 6.7. 6.8. 6.8.1. 6.8.2. 6.8.3. 6.8.4. 6.8.5. 7. 7.1. 7.2. 7.3. 7.3.1. 7.3.2. 7.3.3. 7.3.4. 7.3.5. 7.3.6. 7.3.7. 7.3.8. 7.3.9. 7.3.10. 7.3.11. 7.3.12. 7.3.13. Title Programming the Demodulator and NICAM Decoder Section Short-Programming and General Programming of the Demodulator Part Demodulator Write Registers: Table and Addresses Demodulator Read Registers: Table and Addresses Demodulator Write Registers for Short-Programming: Functions and Values Demodulator Short-Programming AUTO_FM/AM: Automatic Switching between NICAM and FM/AM-Mono Demodulator Write Registers for the General Programming Mode: Functions and Values Register `AD_CV' Register `MODE_REG' FIR Parameter DCO Registers Demodulator Read Registers: Functions and Values Autodetection of Terrestrial TV Audio Standards C_AD_BITS ADD_BITS [10...3] 0038hex CIB_BITS ERROR_RATE 0057hex CONC_CT (for compatibility with MSP 3410B) FAWCT_IST (for compatibility with MSP 3410B) PLL_CAPS AGC_GAIN Sequences to Transmit Parameters and to Start Processing Software Proposals for Multistandard TV Sets Multistandard Including System B/G with NICAM/FM-Mono only Multistandard Including System I with NICAM/FM-Mono only Multistandard Including System B/G with NICAM/FM-Mono and German DUAL-FM Satellite Mode Automatic Search Function for FM Carrier Detection Programming the DSP Section (Audio Baseband Processing) DSP Write Registers: Table and Addresses DSP Read Registers: Table and Addresses DSP Write Registers: Functions and Values Volume - Loudspeaker and Headphone Channel Balance - Loudspeaker and Headphone Channel Bass - Loudspeaker and Headphone Channel Treble - Loudspeaker and Headphone Channel Loudness - Loudspeaker and Headphone Channel Spatial Effects - Loudspeaker Channel Volume - SCART1 and SCART2 Channel Channel Source Modes Channel Matrix Modes SCART Prescale FM/AM Prescale FM Matrix Modes (see also Table 4-1) FM Fixed Deemphasis
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Contents, continued Page 46 47 47 47 47 48 48 48 48 48 49 50 50 50 50 50 51 51 51 51 51 51 52 55 55 57 60 64 66 66 67 71 77 79 80 Section 7.3.14. 7.3.15. 7.3.16. 7.3.17. 7.3.18. 7.3.19. 7.3.20. 7.3.21. 7.3.22. 7.3.23. 7.3.24. 7.3.25. 7.4. 7.5. 7.6. 7.6.1. 7.6.2. 7.6.3. 7.6.4. 7.6.5. 7.6.6. 7.6.7. 8. 9. 9.1. 9.2. 9.3. 9.4. 9.5. 9.5.1. 9.5.2. 9.5.3. 10. 11. 12. Title FM Adaptive Deemphasis NICAM Prescale NICAM Deemphasis I2S1 and I2S2 Prescale ACB Register Beeper Identification Mode FM DC Notch Mode Tone Control Automatic Volume Correction (AVC) Subwoofer Channel Equalizer Loudspeaker Channel Exclusions for the Audio Baseband Features Phase Relationship of Analog Outputs DSP Read Registers: Functions and Values Stereo Detection Register Quasi-Peak Detector DC Level Register MSP Hardware Version Code MSP Major Revision Code MSP Product Code MSP ROM Version Code
PRELIMINARY DATA SHEET
Differences between MSP 3400C, MSP 3400D, MSP 3410B, and MSP 3410D Specifications Outline Dimensions Pin Connections and Short Descriptions Pin Configurations Pin Circuits (pin numbers refer to PLCC68 package) Electrical Characteristics Absolute Maximum Ratings Recommended Operating Conditions Characteristics Application Circuit Appendix A: MSP 34x0D Version History Data Sheet History
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MSP 34x0D
1.1. Common Features of MSP 34x0D - AVC: Automatic Volume Correction - Subwoofer Output - 5-band graphic equalizer (as in MSP 3400C) - Enhanced spatial effect (pseudostereo/basewidth enlargement as in MSP 3400C)
Multistandard Sound Processors Release Notes: The hardware description in this document is valid for the MSP 34x0D version B3 and following versions. Revision bars indicate significant changes to the previous edition.
1. Introduction The MSP 34x0D is designed as a single-chip Multistandard Sound Processor for applications in analog and digital TV sets, satellite receivers, video recorders, and PC cards. The MSP 34x0D, again, improves function integration: The full TV sound processing, starting with analog sound IF signal-in, down to processed analog AF-out, is performed in a single chip. It covers all European TV standards (some examples are shown in Table 3-1). The MSP 3400D is fully pin and software-compatible to the MSP 3410D, but is not able to decode NICAM. It is also compatible to the MSP 3400C. The IC is produced in submicron CMOS technology, combined with high-performance digital signal processing. The MSP 34x0D is available in the following packages: PLCC68, PSDIP64, PSDIP52, PQFP80, and PLQFP64. Note: The MSP 3410D version is fully downward-compatible to the MSP 3410B, the MSP 3400B, and the MSP 3400C. To achieve full software-compatibility with these types, the demodulator part must be programmed as described in the data sheet of the MSP 3410B.
- headphone channel with balance, bass, treble, loudness - balance for loudspeaker and headphone channels in dB units (optional) - D/A converters for SCART2 out - improved oversampling filters (as in MSP 3400C) - Four SCART inputs - Full SCART in/out matrix without restrictions - SCART volume in dB units (optional) - Additional I2S input (as in MSP 3400C) - New FM identification (as in MSP 3400C) - Demodulator short programming - Autodetection for terrestrial TV sound standards - Improved carrier mute algorithm - Improved AM demodulation - ADR together with DRP 3510A - Dolby Pro Logic together with DPL 351xA - Reduction of necessary controlling - Less external components - Significant reduction of radiation
1.2. Specific Features of MSP 3410D - All NICAM standards - Precise bit-error rate indication - Automatic switching from NICAM to FM/AM or viceversa - Improved NICAM synchronization algorithm
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2. Basic Features of the MSP 34x0D 2.1. Demodulator and NICAM Decoder Section The MSP 34x0D is designed to perform demodulation of FM or AM-Mono TV sound. Alternatively, two-carrier FM systems according to the German or Korean terrestrial specs or the satellite specs can be processed with the MSP 34x0D. Digital demodulation and decoding of NICAM-coded TV stereo sound, is done only by the MSP 3410. The MSP 34x0D offers a powerful feature to calculate the carrier field strength which can be used for automatic standard detection (terrestrial) and search algorithms (satellite). The IC may be used in TV sets, as well as in satellite tuners and video recorders. It offers profitable multistandard capability, including the following advantages: - two selectable analog inputs (TV and SAT-IF sources) - Automatic Gain Control (AGC) for analog IF input. Input range: 0.10-3 Vpp - integrated A/D converter for sound-IF inputs - all demodulation and filtering is performed on chip and is individually programmable - easy realization of all digital NICAM standards (B/G, I, L, and D/K) with MSP 3410. - FM demodulation of all terrestrial standards (incl. identification decoding) - FM demodulation of all satellite standards - no external filter hardware is required - only one crystal clock (18.432 MHz) is necessary - FM carrier level calculation for automatic search algorithms and carrier mute function - high-deviation FM-Mono mode (max. deviation: approx. 360 kHz)
ADR 3 Sound IF 1 Sound IF 2 MONO IN SCART1 IN SCART2 IN SCART3 IN SCART4 IN 2 2 2 2 2 2 I2S 5 I2C 2 2 1 2 Loudspeaker OUT Subwoofer OUT Headphones OUT SCART1 OUT SCART2 OUT
PRELIMINARY DATA SHEET
2.2. DSP Section (Audio Baseband Processing) - flexible selection of audio sources to be processed - two digital input and one output interface via I2S bus for external DSP processors, featuring surround sound, ADR etc. - digital interface to process ADR (ASTRA Digital Radio) together with DRP 3510A - performance of all deemphasis systems including adaptive Wegener Panda 1 without external components or controlling - digitally performed FM identification decoding and dematrixing - digital baseband processing: volume, bass, treble, 5-band equalizer, loudness, pseudostereo, and basewidth enlargement - simple controlling of volume, bass, treble, equalizer etc.
2.3. Analog Section - four selectable analog pairs of audio baseband inputs (= four SCART inputs) input level: 2 VRMS, input impedance: 25 k - one selectable analog mono input (i.e. AM sound): input level: 2 VRMS, input impedance: 15 k - two high-quality A/D converters, S/N-Ratio: 85 dB - 20 Hz to 20 kHz bandwidth for SCART-to-SCART copy facilities - MAIN (loudspeaker) and AUX (headphones): two pairs of fourfold oversampled D/A-converters output level per channel: max. 1.4 VRMS output resistance: max. 5 k S/N-ratio: 85 dB at maximum volume max. noise voltage in mute mode: 10 V (BW: 20 Hz ...16 kHz) - two pairs of fourfold oversampled D/A converters supplying two selectable pairs of SCART outputs. output level per channel: max. 2 VRMS, output resistance: max. 0.5 k, S/N-Ratio: 85 dB (20 Hz ... 16 kHz)
MSP 34x0D
Fig. 2-1: Main I/O signals of the MSP 34x0D
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MSP 34x0D
In the case of NICAM/FM (AM) mode, there are three different audio channels available: NICAM A, NICAM B, and FM/AM-Mono. NICAM A and B may belong either to a stereo or to a dual-language transmission. Information about operation mode and the quality of the NICAM signal can be read by the CCU via the control bus. In the case of low quality (high biterror rate), the CCU may decide to switch to the analog FM/AM-Mono sound. Alternatively, an automatic NICAM-FM/AM switching may be applied.
3. Application Fields of the MSP 34x0D In the following sections, a brief overview of the two main TV sound standards, NICAM 728 and German FM-Stereo, demonstrates the complex requirements of a multistandard audio IC.
3.1. NICAM plus FM/AM-Mono According to the British, Scandinavian, Spanish, and French TV standards, high-quality stereo sound is transmitted digitally. The systems allow two high-quality digital sound channels to be added to the already existing FM/AM channel. The sound coding follows the format of the so-called Near Instantaneous Companding System (NICAM 728). Transmission is performed using Differential Quadrature Phase Shift Keying (DQPSK). Table 3-2 provides some specifications of the sound coding (NICAM); Table 3-3 offers an overview of the modulation parameters.
3.2. German 2-Carrier System (Dual-FM System) Since September 1981, stereo and dual-sound programs have been transmitted in Germany using the 2-carrier system. Sound transmission consists of the already existing first sound carrier and a second sound carrier additionally containing an identification signal. More details of this standard are given in Tables 3-1 and 3-4. For D/K and M-Korea, very similar systems are used.
Table 3-1: TV standards TV System B/G B/G L I D/K Position of Sound Carrier /MHz 5.5/5.7421875 5.5/5.85 6.5/5.85 6.0/6.552 6.5/6.2578125 D/K1 6.5/6.7421875 D/K2 6.5/5.85 D/K-NICAM 4.5 4.5/4.724212 6.5 7.02/7.2 Sound Modulation FM-Stereo FM-Mono/NICAM AM-Mono/NICAM FM-Mono/NICAM FM-Stereo FM-Mono/NICAM FM-Mono FM-Stereo FM-Mono FM-Stereo NTSC PAL PAL Color System PAL PAL SECAM-L PAL SECAM-East Country Germany Scandinavia, Spain France UK USSR Hungary USA Korea Europe (ASTRA) Europe (ASTRA)
M M-Korea Satellite Satellite
Note: NICAM demodulation cannot be done with the MSP 3400D
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Table 3-2: Summary of NICAM 728 sound coding characteristics Characteristics Audio sampling frequency Number of channels Initial resolution Companding characteristics Coding for compressed samples Preemphasis Audio overload level Values 32 kHz 2 14 bits/sample
PRELIMINARY DATA SHEET
near instantaneous, with compression to 10 bits/sample in 32-sample (1 ms) blocks 2's complement CCITT recommendation J.17 (6.5 dB attenuation at 800 Hz) +12 dBm measured at the unity gain frequency of the preemphasis network (2 kHz)
Table 3-3: Summary of NICAM 728 sound modulation parameters Specification Carrier frequency of digital sound Transmission rate Type of modulation Spectrum shaping Roll-off factor 1.0 Carrier frequency of analog sound component Power ratio between vision carrier and analog sound carrier Power ratio between analog and modulated digital sound carrier 6.0 MHz FM mono 10 dB 0.4 5.5 MHz FM mono 13 dB I 6.552 MHz B/G 5.85 MHz L 5.85 MHz 728 kbit/s Differentially encoded quadrature phase shift keying (DQPSK) by means of Roll-off filters 1.0 0.4 6.5 MHz AM mono terrestrial 10 dB cable 16 dB 13 dB 0.4 6.5 MHz FM-Mono D/K 5.85 MHz
10 dB
7 dB
17 dB
11 dB
Hungary 12 dB
Poland 7 dB
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PRELIMINARY DATA SHEET
MSP 34x0D
Table 3-4: Key parameters for B/G, D/K, and M 2-carrier sound system Sound Carriers B/G Vision/sound power ratio Sound bandwidth Preemphasis Frequency deviation Sound Signal Components Mono transmission Stereo transmission Dual-sound transmission mono (L+R)/2 language A (L+R)/2 R language B mono (L-R)/2 50 s Carrier FM1 D/K 13 dB 40 Hz to 15 kHz 75 s 50 s 75 s M B/G Carrier FM2 D/K 20 dB M
50 kHz
25 kHz
50 kHz
25 kHz
Identification of Transmission Mode on Carrier FM2 Pilot carrier frequency in kHz Type of modulation Modulation depth Modulation frequency 54.6875 AM 50 % mono: unmodulated stereo: 117.5 Hz dual: 274.1 Hz 149.9 Hz 276.0 Hz 55.0699
33
34 39 MHz
5
9 MHz
According to the mixing characteristics of the sound IF mixer, the sound IF filter may be omitted.
SAW Filter Tuner Sound IF Mixer
Sound IF Filter
Loudspeaker
1
Mono Vision Demodulator SCART1
2
Subwoofer
2
MSP 34x0D
Headphone
SCART Inputs Composite Video
SCART2
2
SCART3 SCART4
2
2 2
SCART1 SCART2
SCART Outputs
I2S1 Dolby Pro Logic Processor DPL35xxA
ADR
I2S2
ADR Decoder DRP3510A
Fig. 3-1: Typical MSP 34x0D application
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4. Architecture of the MSP 34x0D Fig. 4-1 shows a simplified block diagram of the IC. Its architecture is split into three main functional blocks: 1. demodulator and NICAM decoder section 2. digital signal processing (DSP) section performing audio baseband processing 3. analog section containing two A/D-converters, nine D/A-converters, and SCART Switching Facilities.
PRELIMINARY DATA SHEET
4.1. Demodulator and NICAM Decoder Section 4.1.1. Analog Sound IF - Input Section The input pins ANA_IN1+, ANA_IN2+, and ANA_IN- offer the possibility to connect two different sound IF (SIF) sources to the MSP 34x0D. By means of bit [8] of AD_CV (see Table 6-5 on page 25), either terrestrial or satellite sound IF signals can be selected. The analog-to-digital conversion of the preselected sound IF signal is done by an A/D converter whose output is used to control an analog automatic gain circuit (AGC) providing an optimal level for a wide range of input levels. It is possible to switch between automatic gain control and a fixed (setable) input gain. In the optimal case, the input range of the A/D converter is completely covered by the sound IF source. Some combinations of SAW filters and sound IF mixer ICs, however, show large picture components on their outputs. In this case, filtering is recommended. It was found, that the high-pass filters formed by the coupling capacitors at pins ANA_IN1+ and ANA_IN2+ and the IF impedance (as shown in the application diagram) are sufficient in most cases.
I2S_DA_OUT ADR-Bus I2S_DA_IN1
I2S_CL I2S_WS
AUD_CL_OUT
XTAL_OUT
I2S_DA_IN2
XTAL_IN
I2S Interface
Crystal PLL
2
Sound IF
ANA_IN1+ ANA_IN2+
I2S1/2L/R
I2S_L/R LOUDSPEAKER L LOUDSPEAKER R SUBWOOFER
D_CTR_OUT0/1
Demodulator & NICAM Decoder
FM1/AM FM2 NICAM A NICAM B
D/A D/A D/A
DACM_L
Loudspeaker
DACM_R
Mono
MONO_IN
DACM_SUB
IDENT
Subwoofer
DSP
HEADPHONE L
D/A D/A
DACA_L
SC1_IN_L
SCART1
SC1_IN_R
Headphone
DACA_R
HEADPHONE R
SC2_IN_L
A/D A/D
SCARTL
SCART1_L
D/A D/A D/A D/A
SC1_OUT_L
SCART2
SC2_IN_R
SCARTR
SCART 1
SC1_OUT_R
SCART1_R
SC3_IN_L
SCART2_L SCART2_R
SC2_OUT_L
SCART3
SC3_IN_R
SCART 2
SC2_OUT_R
SC4_IN_L
SCART4
SC4_IN_R
SCART Switching Facilities
Fig. 4-1: Architecture of the MSP 34x0D
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MSP 34x0D
4.1.3. Low-pass Filtering Block for Mixed Sound IF Signals Data shaping and/or FM bandwidth limitation is performed by a linear phase finite impulse response (FIR) filter. Just like the oscillators' frequency, the filter coefficients are programmable and are written into the IC by the CCU via the control bus. Thus, for example, different NICAM versions can easily be implemented. Two not necessarily different sets of coefficients are required, one for MSP-Ch1 (NICAM or FM2) and one for MSP-Ch2 (FM1 = FM-mono). In a corresponding table several coefficient sets are proposed.
4.1.2. Quadrature Mixers The digital input coming from the integrated A/D converter may contain audio information at a frequency range of theoretically 0 to 9 MHz corresponding to the selected standards. By means of two programmable quadrature mixers, two different audio sources, for example NICAM and FM-Mono, may be shifted into baseband position. In the following, the two main channels are provided to process either: - NICAM (MSP-Ch1) and FM/AM mono (MSP-Ch2) simultaneously or, alternatively: - FM-Mono (Ch2) - FM2 (MSP-Ch1) and FM1 (MSP-Ch2). Two programmable registers, to be divided up into a low and a high part, determine frequency of the oscillator, which corresponds to the frequency of the desired audio carrier.
DCO1 MODE_REG[6] Oscillator FIR1 Phase Differentiator DQPSK Decoder Phase and AM Discrimination NICAM Decoder MSP3410D only
ADR
NICAMA NICAMB
Mixer VREFTOP
Lowpass
Mute
Lowpass
FM2
MSP sound IF channel 1 (MSP-Ch1: FM2, NICAM)
AD_CV[7:1] ANA_IN1+ AGC ANA_IN2+ AD_CV[8] AD Amplitude
Carrier Detect Mixer AD_CV[9] IDENT
Carrier Detect
ANA_IN-
MSP sound IF channel 2 (MSP-Ch2: FM1, AM)
Mixer Lowpass
Amplitude
Phase and AM Discrimination Phase
Mute Differentiator
Lowpass
FM1/AM
FRAME NICAMA DCO2
Pins Internal signal lines (see fig. 4-2) Demodulator Write Registers DCO2 Oscillator
FIR2
MODE_REG[8]
Fig. 4-2: Architecture of demodulator and NICAM decoder section
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4.1.4. Phase and AM Discrimination The filtered sound IF signals are demodulated by means of the phase and amplitude discriminator block. On the output, the phase and amplitude is available for further processing. AM signals are derived from the amplitude information, whereas the phase information serves for FM and NICAM (DQPSK) demodulation.
PRELIMINARY DATA SHEET
4.1.8. FM Carrier Mute Function in the Dual-Carrier FM Mode To prevent noise effects or FM identification problems in the absence of one of the two FM carriers, the MSP 34x0D offers a carrier detection feature, which must be activated by means of AD_CV[9]. If no FM carrier is available at the MSPD channel 1, the corresponding channel FM2 is muted. If no FM carrier is available at the MSPD channel 2, the corresponding channel FM1 is muted.
4.1.5. Differentiators FM demodulation is completed by differentiating the phase information output.
4.1.9. DQPSK Decoder In case of NICAM mode, the phase samples are decoded according the DQPSK-coding scheme. The output of this block contains the original NICAM bitstream.
4.1.6. Low-pass Filter Block for Demodulated Signals The demodulated FM and AM signals are further lowpass filtered and decimated to a final sampling frequency of 32 kHz. The usable bandwidth of the final baseband signals is about 15 kHz.
4.1.10. NICAM Decoder Before any NICAM decoding can start, the MSP must lock to the NICAM frame structure by searching and synchronizing to the so-called frame alignment words (FAW). To reconstruct the original digital sound samples, the NICAM bitstream has to be descrambled, deinterleaved, and rescaled. Also, bit-error detection and correction (concealment) is performed in this block. To facilitate the Central Control Unit CCU to switch the (e.g.) TV set to the actual sound mode, control information on the NICAM mode and bit error rate are supplied by the NICAM decoder. It can be read out via the I2C bus. An automatic switching facility (AUTO_FM) between NICAM and FM/AM reduces the amount of CCU instructions in case of bad NICAM reception.
4.1.7. High-Deviation FM Mode By means of MODE_REG [9], the maximum FM deviation can be extended to approximately 360 kHz. Since this mode can be applied only for the MSP sound IF channel 2, the corresponding matrices in the baseband processing must be set to sound A. Apart from this, the coefficient sets 380 kHz FIR2 or 500 kHz FIR2 must be chosen for the FIR2. In relation to the normal FM mode, the audio level of the high-deviation mode is reduced by 6 dB. The FM prescaler should be adjusted accordingly. In high-deviation FM mode, neither FM-Stereo nor FM identification nor NICAM processing is possible simultaneously.
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PRELIMINARY DATA SHEET
MSP 34x0D
selected SCART inputs to SCART outputs in the TV set's stand-by mode. In case of power-on start or starting from stand-by, the IC switches automatically to the default configuration, shown in Fig. 4-3. This action takes place after the first I2C transmission into the DSP part. By transmitting the ACB register first, the individual default setting mode of the TV set can be defined.
4.2. Analog Section 4.2.1. SCART Switching Facilities The analog input and output sections include full matrix switching facilities, which are shown in Fig. 4-3. To design a TV set with four pairs of SCART inputs and two pairs of SCART outputs, no external switching hardware is required. The switches are controlled by the ACB bits defined in the audio processing interface (see section 7.3.18. on page 47).
SCART_IN SC1_IN_L/R SC2_IN_L/R SC3_IN_L/R SC4_IN_L/R MONO_IN to Audio Baseband Processing (DSP_IN) A D SCARTL/R ACB[5,9,8]
4.3. DSP Section (Audio Baseband Processing) All audio baseband functions are performed by digital signal processing (DSP). The DSP functions are grouped into three processing parts: input preprocessing, channel source selection, and channel postprocessing (see Fig. 4-5 and section 7.). The input preprocessing is intended to prepare the various signals of all input sources in order to form a standardized signal at the input to the channel selector. The signals can be adjusted in volume, are processed with the appropriate deemphasis, and are dematrixed if necessary. Having prepared the signals that way, the channel selector makes it possible to distribute all possible source signals to the desired output channels. The ability to route in an external coprocessor for special effects, like surround processing and sound field processing, is of special importance. Routing can be done with each input source and output channel via the I2S inputs and outputs. All input and output signals can be processed simultaneously with the exception that FM2 cannot be processed at the same time as NICAM. FM identification and adaptive deemphasis are also not possible simultaneously. Note, that the NICAM input signals are only available in the MSP 3410D version.
Mute
S1
ACB[6,11,10]
SCART_OUT
SC1_OUT_L/R
S2
Mute ACB[7,13,12]
SCART_OUT from Audio Baseband Processing (DSP_OUT) D A SCART1_L/R D A SCART2_L/R Mute SC2_OUT_L/R
4.3.1. Dual-Carrier FM Stereo/Bilingual Detection For the terrestrial dual-FM carrier systems, audio information can be transmitted in three modes: mono, stereo, or bilingual. To obtain information about the current audio operation mode, the MSP 34x0D detects the socalled identification signal. Information is supplied via the Stereo Detection Register to an external CCU.
Stereo Detection Filter IDENT AM Demodulation Bilingual Detection Filter Level Detect Level Detect Stereo Detection Register
S3
Fig. 4-3: SCART switching facilities (see 7.3.18.). Switching positions show the default configuration after power-on reset
4.2.2. Stand-by Mode If the MSP 34x0D is switched off by first pulling STANDBYQ low, and then disconnecting the 5 V, but keeping the 8 V power supply (`Stand-by'-mode), the switches S1, S2, and S3 (see Fig. 4-3) maintain their position and function. This facilitates the copying from
-
Fig. 4-4: Stereo/bilingual detection
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Channel Source Select
14
Analog Inputs SCARTL SCARTR SCART Prescale Loudspeaker Channel Matrix AVC Bass/ Treble or Equalizer
MSP 34x0D
Loudness
Complementary Highpass
Loudspeaker L Spatial Effects Balance Loudspeaker R Level Adjust Volume Subwoofer Loudspeaker Outputs
DC level readout FM1 FM1/AM Adaptive Deemphasis FM2 Demodulated IF Inputs NICAMA Deemphasis J17 NICAMB Prescale FM/AM FM-Matrix Prescale Headphone Channel Matrix Beeper
Lowpass
Deemphasis 50/75 s J17
DC level readout FM2
Volume Bass/ Treble
Headphone L Headphone R
Loudness
Balance
Headphone Outputs
NICAM SCART1 Channel Matrix Volume SCART1_L SCART1_R SCART Outputs SCART2 Channel Matrix Volume SCART2_L SCART2_R
I2S1L I2S1R I2S Bus Inputs I S2L I S2R
2 2
I2S1 Prescale
I S2 Prescale
2
I 2S Channel Matrix
I2SL I2SR
I2S Outputs
Quasi-Peak Channel Matrix NICAMA Internal signal lines (see Fig. 4-2 and Fig. 4-3)
Quasi peak readout L Quasi-Peak Detector Quasi peak readout R
Fig. 4-5: Audio baseband processing (DSP firmware) PRELIMINARY DATA SHEET
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PRELIMINARY DATA SHEET
MSP 34x0D
Table 4-1: Some examples for recommended channel assignments for demodulator and audio processing part Mode
B/G-Stereo B/G-Bilingual
MSP Sound IFChannel 1
FM2 (5.74 MHz): R FM2 (5.74 MHz): Sound B
MSP Sound IFChannel 2
FM1 (5.5 MHz): (L+R)/2 FM1 (5.5 MHz): Sound A
FMMatrix
B/G Stereo No Matrix
ChannelSelect
Speakers: FM Speakers: FM H. Phone: FM Speakers: NICAM H. Phone: FM Speakers: FM Speakers: FM Speakers: FM H. Phone: FM Speakers: FM H. Phone: FM
Channel Matrix
Stereo Speakers: Sound A H. Phone: Sound B Speakers: Stereo H. Phone: Sound A Sound A Stereo Speakers: Sound A H. Phone: Sound B=C Speakers: Sound A H. Phone: Sound A
NICAM-I-ST/ FM-mono Sat-Mono Sat-Stereo Sat-Bilingual
NICAM (6.552 MHz)
FM (6.0 MHz): mono
No Matrix
not used 7.2 MHz: R 7.38 MHz: Sound C
FM (6.5 MHz): mono 7.02 MHz: 7.02 MHz: L Sound A
No Matrix No Matrix No Matrix
Sat-High Dev. Mode
don't care
6.552 MHz
No Matrix
4.4. Audio PLL and Crystal Specifications The MSP 34x0D requires a 18.432 MHz (12 pF, parallel) crystal. The clock supply of the whole system depends on the MSP 34x0D operation mode: 1. FM-Stereo, FM-Mono: The system clock runs free on the crystal's 18.432 MHz. 2. NICAM: An integrated clock PLL uses the 364 kHz baud rate, accomplished in the NICAM demodulator block to lock the system clock to the bit rate, respectively, 32-kHz sampling rate of the NICAM transmitter. As a result, the whole audio system is supplied with a controlled 18.432 MHz clock. 3. I S slave operation: In this case, the system clock is locked to a synchronizing signal (I2S_CL, I2S_WS) supplied by the coprocessor chip. Remark on using the crystal: External capacitors at each crystal pin to ground are required (see General Crystal Recommendations on page 69).
2
4.5. ADR Bus Interface For the ASTRA Digital Radio System (ADR), the MSP 34x0D performs preprocessing, as there are carrier selection and filtering. Via the 3-line ADR bus, the resulting signals are transferred to the DRP 3510A, where the source decoding is performed. To be prepared for an upgrade to ADR with an additional DRP board, the following lines of MSP 34x0D should be provided on a feature connector: - AUD_CL_OUT - I2S_DA_IN1 or I2S_DA_IN2 - I2S_DA_OUT - I2S_WS - I2S_CLK - ADR_CL - ADR_WS - ADR_DA
4.6. Digital Control Output Pins The static level of two output pins of the MSP 34x0D (D_CTR_OUT0/1) is switchable between HIGH and LOW by means of the I2C bus. This enables the controlling of external hardware-controlled switches or other devices via I2C bus (see section 7.3.18. on page 47).
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MSP 34x0D
4.7. I2S Bus Interface By means of this standardized interface, additional feature processors can be connected to the MSP 34x0D. Two possible formats are supported: The standard mode (MODE_REG[4]=0) selects the SONY format, where the I2S_WS signal changes at the word boundaries. The so-called PHILIPS format, which is characterized by a change of the I2S_WS signal one I2S_CL period before the word boundaries, is selected by setting MODE_REG[4]=1. The MSP 34x0D normally serves as the master on the I2S interface. Here, the clock and word strobe lines are driven by the MSP 34x0D. By setting MODE_REG[3]=1, the MSP 34x0D is switched to a slave mode. Now, these lines are input to the MSP 34x0D and the master clock is synchronized to 576 times the I2S_WS rate (32 kHz). NICAM operation is not possible in this mode.
PRELIMINARY DATA SHEET
The I2S bus interface consists of five pins: 1. I2S_DA_IN1, I2S_DA_IN2: For input, four channels (two channels per line, 2*16 bits) per sampling cycle (32 kHz) are transmitted. 2. I2S_DA_OUT: For output, two channels (2*16 bits) per sampling cycle (32 kHz) are transmitted. 3. I2S_CL: Gives the timing for the transmission of I2S serial data (1.024 MHz). 4. I2S_WS: The I2S_WS word strobe line defines the left and right sample. A precise I2S timing diagram is shown in Fig. 4-6.
(Data: MSB first)
FI2SWS I2S_WS
SONY Mode PHILIPS Mode PHILIPS/SONY Mode programmable by MODE_REG[4] I2S_CL Detail A I2S_DAIN
R LSB L MSB
SONY Mode PHILIPS Mode Detail C
L LSB R MSB
R LSB L LSB
16 bit left channel Detail B I2S_DAOUT
R LSB L MSB L LSB R MSB
16 bit right channel
R LSB L LSB
16 bit left channel
16 bit right channel
Detail C
I2S_CL
1/FI2SCL
Detail A,B
I2S_CL
TI2SWS1
TI2SWS2
TI2S1
TI2S2
I2S_WS as INPUT TI2S5 TI2S6
I2S_DA_IN TI2S3 TI2S4
I2S_WS as OUTPUT
I2S_DA_OUT
Fig. 4-6: I2S bus timing diagram
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PRELIMINARY DATA SHEET
MSP 34x0D
Due to the internal architecture of the MSP 34x0D, the IC cannot react immediately to an I2C request. The typical response time is about 0.3 ms for the DSP processor part and 1 ms for the demodulator part if NICAM processing is active. If the receiver (MSP) can't receive another complete byte of data until it has performed some other function; for example, servicing an internal interrupt, it can hold the clock line I2C_CL LOW to force the transmitter into a wait state. The positions within a transmission where this may happen are indicated by 'Wait' in section 5.1. The maximum wait period of the MSP during normal operation mode is less than 1 ms. I2C bus error caused by MSP hardware problems: In case of any internal error, the MSPs wait period is extended to 1.8 ms. Afterwards, the MSP does not acknowledge (NAK) the device address. The data line will be left HIGH by the MSP and the clock line will be released. The master can then generate a STOP condition to abort the transfer. By means of NAK, the master is able to recognize the error state and to reset the IC via I2C bus. While transmitting the reset protocol (see section 5.2.4. on page 19) to `CONTROL', the master must ignore the notacknowledge bits (NAK) of the MSP. A general timing diagram of the I2C Bus is shown in Fig. 5-2 on page 19.
5. I2C Bus Interface: Device and Subaddresses As a slave receiver, the MSP 34x0D can be controlled via I2C bus. Access to internal memory locations is achieved by subaddressing. The demodulator and the DSP processor parts have two separate subaddressing register banks. In order to allow for more MSP 34x0D ICs to be connected to the control bus, an ADR_SEL pin has been implemented. With ADR_SEL pulled to HIGH, LOW, or left open, the MSP 34x0D responds to changed device addresses. Thus, three identical devices can be selected. By means of the RESET bit in the CONTROL register, all devices with the same device address are reset. The IC is selected by asserting a special device address in the address part of an I2C transmission. A device address pair is defined as a write address (80, 84, or 88hex) and a read address (81, 85, or 89hex) (see Table 5-1). Writing is done by sending the device write address, followed by the subaddress byte, two address bytes, and two data bytes. Reading is done by sending the device write address, followed by the subaddress byte and two address bytes. Without sending a stop condition, reading of the addressed data is completed by sending the device read address (81, 85, or 89hex) and reading two bytes of data (see Fig. 5-1: "I2C Bus Protocol" and section 5.2. "Proposal for MSP 34x0D I2C Telegrams").
Table 5-1: I2C Bus Device Addresses ADR_SEL Mode MSP device address Write 80 hex Low Read 81 hex Write 84 hex High Read 85 hex Write 88 hex Left Open Read 89 hex
Table 5-2: I2C Bus Subaddresses Name CONTROL TEST WR_DEM RD_DEM WR_DSP RD_DSP Binary Value 0000 0000 0000 0001 0001 0000 0001 0001 0001 0010 0001 0011 Hex Value 00 01 10 11 12 13 Mode W W W W W W Function software reset only for internal use write address demodulator read address demodulator write address DSP read address DSP
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MSP 34x0D
Table 5-3: Control Register (Subaddress: 00 hex) Name CONTROL Subaddress 00 hex MSB 1 : RESET 0 : normal 14 0 13..1 0
PRELIMINARY DATA SHEET
LSB 0
5.1. Protocol Description
Write to DSP or Demodulator
S write device address Wait ACK subaddr ACK addr byte high ACK addr byte low ACK data byte high ACK data byte low ACK P
Read from DSP or Demodulator
S write device address Wait ACK subaddr ACK addr byte high ACK addr byte low ACK S read device address Wait ACK data byte high ACK data byte low NAK P
Write to Control or Test Registers
S write device address Wait ACK subaddr ACK data byte high ACK data byte low ACK P
Note: S = P= ACK = NAK = Wait =
I2C bus Start Condition from master I2C bus Stop Condition from master Acknowledge-Bit: LOW on I2C_DA from slave (=MSP, gray) or master (=CCU, hatched) Not-Acknowledge Bit: HIGH on I2C_DA from master (=CCU, hatched) to indicate `End of Read' or from MSP indicating internal error state I2C clock line held low by the slave (=MSP) while interrupt is serviced (<1.8 ms)
I2C_DA S I2C_CL Fig. 5-1: I2C bus protocol
1 0 P
(MSB first; data must be stable while clock is high)
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PRELIMINARY DATA SHEET
MSP 34x0D
(Data: MSB first) 1 fI2C I2C_CL TI2C4 TI2C3
TI2C1 I2C_DA as input
TI2C5
TI2C6
TI2C2
TI2COL2 I2C_DA as output
TI2COL1
Fig. 5-2: I2C bus timing diagram
5.2. Proposal for MSP 34x0D I2C Telegrams 5.2.1. Symbols daw dar < > aa dd write device address read device address start condition stop condition address byte data byte
5.2.2. Write Telegrams write to CONTROL register write data into demodulator write data into DSP
5.2.3. Read Telegrams read data from demodulator read data from DSP
5.2.4. Examples <80 00 80 00> <80 00 00 00> <80 12 00 08 01 20> RESET MSP statically clear RESET set loudspeaker channel source to NICAM and matrix to STEREO
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MSP 34x0D
5.3. Start-Up Sequence: Power-Up and I2C-Controlling After power-on or RESET (see Fig. 5-3), the IC is in an inactive state. The CCU has to transmit the required coefficient set for a given operation via the I2C bus. Initialization should start with the demodulator part. If required for any reason, the audio processing part can be loaded before the demodulator part.
PRELIMINARY DATA SHEET
DVSUP AVSUP
4.5 V
t/ms
RESETQ
0.7xDVSUP
Low-to-High Threshold
0.45...0.55xDVSUP High-to-Low Threshold
t/ms
Reset Delay >2 ms
Internal Reset
High
Low
t/ms
Power-Up Reset: Threshold and Timing (Note: 0.7xDVSUP means 3.5 Volt with DVSUP=5.0 Volt) Fig. 5-3: Power-up sequence
Note: The reset should not reach high level before the oscillator has started. This requires a reset delay of >2 ms
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PRELIMINARY DATA SHEET
MSP 34x0D
6. Programming the Demodulator and NICAM Decoder Section 6.1. Short-Programming and General Programming of the Demodulator Part The demodulator part of the MSP 34x0D can be programmed in two different modes: 1. Demodulator Short-Programming provides a comfortable way to set up the demodulator for many terrestrial TV sound standards with one single I2C bus transmission. The coding is listed in section 6.4.1. If a parameter does not coincide with the individual programming concept, it simply can be overwritten by using the General Programming Mode. Some bits of the registers AD_CV (see section 6.5.1. on page 25) and MODE_REG (see section 6.5.2. on page 27) are not affected by the short-programming. They must be transmitted once if their reset status does not fit. The Demodulator Short-Programming is not compatible to MSP 3410B and MSP 3400C. Autodetection for terrestrial TV standards is part of the Demodulator Short-Programming. This feature enables the detection and set-up of the actual TV sound standard within 0.5 s. Since the detected standard is readable by the control processor, the Autodetection feature is mainly recommended for the primary set-up of a TV set: after having once determined the corresponding TV channels, their sound standards can be stored and later on programmed by the Demodulator Short-Programming (see section 6.4.1. on page 23 and section 6.6.1. on page 32). 2. General Programming ensures the software-compatibility to other MSPs. It offers a very flexible way to apply all of the MSP 34x0D demodulator facilities. All registers except 0020hex (Demodulator Short-Programming) have to be written with values corresponding to the individual requirements. For satellite applications, with their many variations, this mode must be selected. All transmissions on the control bus are 16 bits wide. However, data for the demodulator part have only 8 or 12 significant bits. These data have to be inserted LSB-bound and filled with zero bits into the 16-bit transmission word. Table 4-1 explains how to assign FM carriers to the MSP Sound IF channels and the corresponding matrix modes in the audio processing part.
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MSP 34x0D
6.2. Demodulator Write Registers: Table and Addresses
PRELIMINARY DATA SHEET
Table 6-1: Demodulator Write Registers; Subaddress: 10hex; these registers are not readable! Demodulator Write Registers Demodulator ShortProgramming AUTO_FM/AM Address (hex) 0020 Function Write into this register to apply Demodulator Short Programming (see section 6.4.1. on page 23). If the internal setting coincidences with the individual requirements no more of the remaining Demodulator Write Registers have to be transferred. Only for NICAM: Automatic switching between NICAM and FM/AM in case of bad NICAM reception (see section 6.4.2. on page 24)
0021
Write Registers necessary for General Programming Mode only AD_CV MODE_REG FIR1 FIR2 DCO1_LO DCO1_HI DCO2_LO DCO2_HI PLL_CAPS 00BB 0083 0001 0005 0093 009B 00A3 00AB 001F input selection, configuration of AGC, Mute Function and selection of A/D converter, FM Carrier Mute on/off mode register filter coefficients channel 1 (6 x 8 bit) filter coefficients channel 2 (6 x 8 bit), + 3 x 8 bit offset (total 72 bits) increment channel 1 low part increment channel 1 high part increment channel 2 low part increment channel 2 high part switchable PLL capacitors to tune open-loop frequency; to use only if NICAM of MODE_REG = 0 ; normally not of interest for the customer
6.3. Demodulator Read Registers: Table and Addresses Table 6-2: Demodulator Read Registers; Subaddress: 11hex; these registers are not writable! Demodulator Read Registers Result of Autodetection C_AD_BITS ADD_BITS CIB_BITS ERROR_RATE CONC_CT FAWCT_IST PLL_CAPS AGC_GAIN Address (hex) 007E 0023 0038 003E 0057 0058 0025 021F 021E Function (see Table 6-13) NICAM Sync bit, NICAM C bits, and three LSBs of additional data bits NICAM: bit [10:3] of additional data bits NICAM: CIB1 and CIB2 control bits NICAM error rate, updated with 182 ms only to be used in MSPB compatibility mode only to be used in MSPB compatibility mode Not for customer use. Not for customer use.
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PRELIMINARY DATA SHEET
MSP 34x0D
6.4. Demodulator Write Registers for Short-Programming: Functions and Values In the following, the functions of some registers are explained and their (default) values are defined:
6.4.1. Demodulator Short-Programming Table 6-3: MSP 34x0D Demodulator Short-Programming Demodulator Short-Programming TV Sound Standard Description Code (hex) AD_CV2)
(see Table 6-5)
0020hex
Internal Setting MODE_ REG2)
(see Table 6-8)
DCO1 (MHz)
DCO2 (MHz)
FIR1/2 Coefficients
Identification Mode
Autodetection M Dual-FM B/G Dual-FM D/K1 Dual-FM D/K2 Dual-FM
0001 0002 0003 0004 0005 0006/ 0007
Detects and sets one of the standards listed below, if available. Results are to be read out of the demodulator read register "Result of Autodetection" (section 6.6.1.) AD_CV- FM AD_CV-FM AD_CV-FM AD_CV-FM M1 M1 M1 M1 4.72421 5.74218 6.25781 6.74218 4.5 5.5 6.5 6.5 AUTO_ FM/AM 5.5 6.5 6.0 6.5 see Table 6-11: Terrestrial TV Standards
1)
Reset, then Standard M see Table 6-11: Terrestrial TV Standards Reset, then Standard B/G
reserved for future dual-FM standards AD_CV-FM AD_CV-AM AD_CV-FM AD_CV-FM M2 M3 M2 M2 5.85 5.85 6.552 5.85
B/G NICAM FM L NICAM AM I NICAM FM D/K NICAM FM
0008 0009 000A 000B >000B
reserved for future NICAM Standards
1) 2)
corresponds to the actual setting of AUTO_FM (Address = 0021hex) bits of AD_CV or MODE_REG, which are not affected by the short-programming, must be transmitted separately if their reset status does not fit.
Note: All parameters in the DSP section (Audio Baseband Processing), except the identification mode register, are not affected by the Demodulator Short-Programming. They still have to be defined by the control processor.
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6.4.2. AUTO_FM/AM: Automatic Switching between NICAM and FM/AM-Mono In case of bad NICAM transmission or loss of the NICAM carrier, the MSPD offers a comfortable mode to switch back to the FM/AM-Mono signal. If automatic switching is active, the MSP internally evaluates the ERROR_RATE. All output channels which are assigned to the NICAM source are switched back to the FM/AM-Mono source without any further CCU instruction, if the NICAM carrier fails or the ERROR_RATE exceeds the definable threshold. Note, that the channel matrix of the corresponding output channels must be set according to the NICAM mode and need not be changed in the FM/AM fall-back case. An appropriate hysteresis algorithm avoids oscillating effects. The MSB of the Register C_AD_BITS (Addr: 0023hex) informs about the actual NICAM FM/AM Status (see section 6.6.2. on page 32).
PRELIMINARY DATA SHEET
There are two possibilities to define the threshold deciding for NICAM or FM/AM-Mono (see Table 6-4): 1. default value of the MSPD (internal threshold = 700, i.e. switch to FM/AM if ERROR_RATE > 700) 2. definable by the customer (recommendable range: threshold = 50...2000, i.e. Bits [10...1] = 25...1000). Note: The auto_FM feature is only active if the NICAM bit of MODE_REG is set.
Table 6-4: Coding of automatic NICAM FM/AM switching (reset status: mode 0) Mode 0 default 1 Auto_FM [11...0] Addr. = 0021hex Bit [0] =0 Bits [11...1] = 0 Bit Bit Bit Bit Bit 3 Bit Bit [0] =1 [11...1] = 0 [0] =1 [10...1] = 25..1000 int = threshold/2 [11] =0 [11] = [0] = 1 [10...1] = 0 Selected Sound at the NICAM Channel Select always NICAM Threshold none Comment Compatible to MSP 3410B, i.e. automatic switching is disabled automatic switching with internal threshold automatic switching with external threshold
NICAM or FM/AM, depending on ERROR_RATE NICAM or FM/AM, depending on ERROR_RATE always FM/AM
700 dec
2
set by customer
none
Forced FM-Mono mode, i.e. automatic switching is disabled
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PRELIMINARY DATA SHEET
MSP 34x0D
6.5. Demodulator Write Registers for the General Programming Mode: Functions and Values 6.5.1. Register `AD_CV' Table 6-5: AD_CV Register (reset status: all bits are "0") AD_CV 00BBhex Bit AD_CV [0] AD_CV [6...1] Meaning not used Reference level in case of Automatic Gain Control = on (see Table 6-6). Constant gain factor when Automatic Gain Control = off (see Table 6-7) Determination of Automatic Gain or Constant Gain Selection of Sound IF source MSP Carrier Mute Function (Must be switched off in High Deviation Mode) AD_CV [15...10] not used 0 = constant gain 1 = automatic gain 0 = ANA_IN1+ 1 = ANA_IN2+ 0 = off: no mute 1 = on: mute as described in section 4.1.8. on page 12 must be set to 0 Settings must be set to 0 Set by Short-Programming AD_CV-FM 0 101000 AD_CV-AM 0 100011
AD_CV [7] AD_CV [8] AD_CV [9]
1 not affected 1
1 not affected 0
000000
000000
Table 6-6: Reference values for active AGC (AD_CV[7] = 1) Application Input Signal Contains AD_CV [6...1] Ref. Value AD_CV [6...1] (dec) Range of Input Signal at pin ANA_IN1+ and ANA_IN2+
Terrestrial TV Dual-Carr. FM NICAM/FM NICAM/AM 2 FM Carriers 1 FM and 1 NICAM Carrier 1 AM and 1 NICAM Carrier 101000 101000 100011 40 40 35 0.10 - 3 Vpp1) 0.10 - 3 Vpp1) 0.10 - 1.4 Vpp recommended: 0.10 - 0.8 Vpp NICAM only SAT ADR
1)
1 NICAM Carrier only 1 or more FM Carriers FM a. ADR carriers
010100 100011
20 35
0.05 - 1.0 Vpp 0.10 - 3 Vpp1)
see DRP 3510A data sheet
For signals above 1.4 Vpp, the minimum gain of 3 dB is switched and overflow of the A/D converter may result. Due to the robustness of the internal processing, the IC works up to and even more than 3 Vpp, if norm conditions of FM/NICAM or FM1/FM2 ratio are supposed. In this overflow case, a loss of FM S/N ratio of about 10 dB may appear.
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Table 6-7: AD_CV parameters for constant input gain (AD_CV[7]=0) Step 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1)
PRELIMINARY DATA SHEET
AD_CV [6...1] Constant Gain 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100
Gain 3.00 dB 3.85 dB 4.70 dB 5.55 dB 6.40 dB 7.25 dB 8.10 dB 8.95 dB 9.80 dB 10.65 dB 11.50 dB 12.35 dB 13.20 dB 14.05 dB 14.90 dB 15.75 dB 16.60 dB 17.45 dB 18.30 dB 19.15 dB 20.00 dB
Input Level at pin ANA_IN1+ and ANA_IN2+ maximum input level: 3 Vpp (FM) or 1 Vpp (NICAM)1)
maximum input level: 0.14 Vpp
For signals above 1.4 Vpp, the minimum gain of 3 dB is switched and overflow of the A/D converter may result. Due to the robustness of the internal processing, the IC works up to and even more than 3 Vpp, if norm conditions of FM/NICAM or FM1/FM2 ratio are supposed. In this overflow case, a loss of FM S/N ratio of about 10 dB may appear.
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PRELIMINARY DATA SHEET
MSP 34x0D
6.5.2. Register `MODE_REG' The register `MODE_REG' contains the control bits determining the operation mode of the MSP 34x0D; Table 6-8 explains all bit positions.
Table 6-8: Control word `MODE_REG'; reset status: all bits are "0" MODE_REG 0083hex Bit [0] [1] [2] Function not used DCTR_TRI I2S_TRI Digital control out 0/1 tri-state I2S outputs tri-state (I2S_CL, I2S_WS, I2S_DA_OUT) Master/Slave mode of the I2S bus WS due to the Sony or Philips Format Switch Audio_Clock_Output to tri-state Mode of MSP-Ch1 Comment Definition 0 : strongly recommended 0 : active 1 : tri-state 0 : active 1 : tri-state 0 : Master 1 : Slave 0 : Sony 1 : Philips 0 : on 1 : tri-state 0 : FM 1 : Nicam 0 : strongly recommended Mode of MSP Ch2 High Deviation Mode (channel matrix must be sound A) 0 : FM 1 : AM 0 : normal 1 : high deviation mode 0 : strongly recommended see also Table 6-11 see also Table 6-11 Mode of MSP Ch1/ ADR Interface Gain for AM Demodulation 0 : Gain = 6 dB 1 : Gain = 0 dB 0 : use FIR1 1 : use FIR2 0 : normal mode/tri-state 1 : ADR mode/active 0 : 0 dB (default. of MSPB) 1 : 12 dB (recommended) Set by Short-Programming M1 0 X X M2 0 X X M3 0 X X
[3] [4] [5]
I2S Mode1) I2S_WS Mode AUD_CL_OUT
X X X
X X X
X X X
[6] [7] [8] [9]
NICAM1) not used FM AM HDEV
0 0 0 0
1 0 0 0
1 0 1 0
[11...10] [12] [13] [14] [15]
1)
not used MSP Ch1 Gain FIR1 Filter Coeff. Set ADR AM Gain
00 0 1 0 1
00 0 0 0 1
00 0 0 0 1
In case of NICAM operation, I2S slave mode is not possible. In case of I2S slave mode, no synchronization to NICAM is allowed.
X: not affected by short-programming
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Table 6-9: Channel modes `MODE_REG [6, 8, 9]' NICAM Bit[6] 1 1 0 0 FM AM Bit[8] 0 1 0 0 HDEV Bit[9] 0 0 0 1 MSP Ch1 NICAM NICAM FM2
PRELIMINARY DATA SHEET
MSP Ch2 FM1 AM FM1 High-Deviation FM
-:-
6.5.3. FIR Parameter The following data values (see Table 6-10) are to be transferred 8 bits at a time embedded LSB-bound in a 16-bit word. The loading sequences must be obeyed. To change a coefficient set, the complete block FIR1 or FIR2 must be transmitted. Note: For compatibility with MSP 3410B, IMREG1 and IMREG2 have to be transmitted. The value for IMREG1 and IMREG2 is 004. Due to the partitioning to 8-bit units, the values 04hex, 40hex, and 00hex arise.
Table 6-10: Loading sequence for FIR coefficients
FIR1 0001hex No. (MSP Ch1: NICAM/FM2) Bits 8 8 8 see Table 6-11 4 5 6 NICAM/FM2_Coeff. (2) NICAM/FM2_Coeff. (1) NICAM/FM2_Coeff. (0) 8 8 8 Value
Symbol Name NICAM/FM2_Coeff. (5) NICAM/FM2_Coeff. (4) NICAM/FM2_Coeff. (3)
1
2 3
FIR2 0005hex No. 1 2 3 4 5 6 7 8 9
(MSP Ch2: FM1/AM ) Bits 8 8 8 8 8 8 see Table 6-11 8 8 8 Value 04hex 40hex 00hex
Symbol Name IMREG1 IMREG1 / IMREG2 IMREG2 FM/AM_Coef (5) FM/AM_Coef (4) FM/AM_Coef (3) FM/AM_Coef (2) FM/AM_Coef (1) FM/AM_Coef (0)
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PRELIMINARY DATA SHEET
MSP 34x0D
Table 6-11: 8-bit FIR coefficients (decimal integer) for MSP 34x0D (reset status: all coefficients are "0")
Coefficients for FIR1 0001hex and FIR2 0005hex
FM Satellite FIR filter corresponds to a band-pass with a bandwidth of B = 130 to 500 kHz
Terrestrial TV Standards
B fc frequency
B/G-, D/KNICAM-FM Coef(i) 0 1 2 3 4 5 ModeREG[12] ModeREG[13] FIR1 FIR2 3 18 27 48 66 72 0
INICAM-FM FIR1 2 4 FIR2 3 18 27 48 66 72 0
LNICAM-AM FIR1 FIR2
B/G-, D/K-, M-Dual FM FIR2 3 18 27 48 66 72 0
130 kHz FIR2 73 53 64 119 101 127 1
180 kHz FIR2 9 18 28 47 55 64 1
200 kHz FIR2 3 18 27 48 66 72 1
280 kHz FIR2
380 kHz FIR2
500 kHz FIR2
Autosearch FIR2
-2 -8 -10
10 50 86
-2 -8 -10
10 50 86 0
-4 -12 -9
23 79 126
-8 -8
4 36 78 107 1
-1 -9 -16
5 65 123 1
-1 -1 -8
2 59 126 1
-1 -1 -8
2 59 126 0
-6 -4
40 94
0
0
0
1
1
1
1
1
1
1
0
For compatibility, except for the FIR2 AM and the autosearch sets, the FIR filter programming as used for the MSP 3410B is also possible. ADR coefficients are listed in the DRP data sheet.
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6.5.4. DCO Registers For a chosen TV standard, a corresponding set of 24-bit registers determining the mixing frequencies of the quadrature mixers, has to be written into the IC. In Table 6-12, some examples of DCO registers are listed. It is necessary to divide them up into low part and high part. The formula for the calculation of the registers for any chosen IF frequency is as follows: INCRdec = int(f / fs 224) with: int f fS = integer function = IF frequency in MHz = sampling frequency (18.432 MHz)
PRELIMINARY DATA SHEET
Conversion of INCR into hex format and separation of the 12-bit low and high parts lead to the required register values (DCO1_HI or _LO for MSP Ch1, DCO2_HI or LO for MSP Ch2).
Table 6-12: DCO registers for the MSP 34x0D (reset status: DCO_HI/LO = "0000") DCO1_LO 0093hex, DCO1_HI 009Bhex ; DCO2_LO 00A3hex, DCO2_HI 00ABhex Freq. [MHz] 4.5 5.04 5.5 5.58 5.7421875 6.0 6.2 6.5 6.552 7.02 7.38 DCO_HIhex 03E8 0460 04C6 04D8 04FC 0535 0561 05A4 05B0 0618 0668 DCO_LOhex 0000 0000 038E 0000 00AA 0555 0C71 071C 0000 0000 0000 5.76 5.85 5.94 6.6 6.65 6.8 7.2 7.56 0500 0514 0528 05BA 05C5 05E7 0640 0690 0000 0000 0000 0AAA 0C71 01C7 0000 0000 Freq. [MHz] DCO_HIhex DCO_LOhex
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PRELIMINARY DATA SHEET
MSP 34x0D
6.6. Demodulator Read Registers: Functions and Values All registers except C_AD_BITS are 8 bits wide. They can be read out of the RAM of the MSP 34x0D. All transmissions take place in 16-bit words. The valid 8 bit data are the 8 LSBs of the received data word. To enable appropriate switching of the channel select matrix of the baseband processing part, the NICAM or FM identification parameters must be read and evaluated by the CCU. The FM identification registers are described in section 7.2. on page 39. To handle the NICAM sound and to observe the NICAM quality, at least the registers C_AD_BITS and ERROR_RATE must be read and evaluated by the CCU. Additional data bits and CIB bits, if supplied by the NICAM transmitter, can be obtained by reading the registers ADD_BITS and CIB_BITS. Observing the presence and quality of NICAM can be delegated to the MSP 3410D, if the automatic switching feature (AUTO_FM, section 6.6.1. on page 32) is applied.
Table 6-13: Result of Autodetection Result of Autodetect Code (Data) hex >07FF 0000 0002 0003 0008 007Ehex
Detected TV Sound Standard Note: After detection, the detected standard is set automatically according to Table 6-3. autodetect still active no TV sound standard was detected; select sound standard manually M Dual FM, even if only FM1 is available B/G Dual FM, even if only FM1 is available B/G FM NICAM, only if NICAM is available L_AM NICAM, whenever a 6.5-MHz carrier is detected, even if NICAM is not available. If also D/K might be possible, a decision has to be made according to the video mode: Video = SECAM_EAST
0009
CAD_BITS[0] = 0 Video = SECAM_L no more activities necessary
CAD_BITS[0] = 1
To be set by means of the short programming mode: D/K1 or D/K2 (see section 6.6.1.) D/K-NICAM (standard 00Bhex)
000A
I-FM-NICAM, even if NICAM is not available
Note: Similar as for the Demodulator Short-Programming, the Autodetection does not affect most of the parameters of the DSP section (Audio Baseband Processing): The following exceptions are to be considered: - identification mode: Autodetection resets and sets the corresponding identification mode - Prescale FM/AM and FM matrix and Deemphasis FM are undefined after Autodetection
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6.6.1. Autodetection of Terrestrial TV Audio Standards By means of Autodetect, the MSP 34x0D offers a simple and fast (<0.5 s) facility to detect the actual TV audio standard. The algorithm checks for the FMMono and NICAM carriers of all common TV sound standards. The following notes must be considered when applying the Autodetect feature: 1. Since there is no way to distinguish between AM and FM carrier, a carrier detected at 6.5 MHz is interpreted as an AM carrier. If video detection results in SECAM East, the MSPD result "9" of Autodetect must be reinterpreted as "Bhex" in case of CAD_BITS[0] = 1, or as "4" or "5" by using the demodulator short programming mode. A simple decision can be made between the two D/K FM stereo standards by setting D/K1 and D/K2 using the short programming mode and checking the identification of both versions (see Table 6-13 on page 31). 2. During active Autodetect, no I2C transfers besides reading the autodetect result are recommended. Results exceeding 07FFhex indicate an active autodetect. 3. The results are to be understood as static information, i.e. no evaluation of FM or NICAM identification concerning the dynamic mode (stereo, bilingual, or mono) are done. 4. Before switching to Autodetect, the audio processing part should be muted. Do not forget to demute after having received the result.
PRELIMINARY DATA SHEET
Table 6-14: NICAM operation modes as defined by the EBU NICAM 728 specification
C4 0 0 0 C3 0 0 0 C2 0 0 1 C1 0 1 0 Operation Mode Stereo sound (NICAM A/B), independent mono sound (FM1) Two independent mono signals (NICAM A, FM1) Three independent mono channels (NICAM A, NICAM B, FM1) Data transmission only; no audio Stereo sound (NICAM A/B), FM1 carries same channel One mono signal (NICAM A). FM1 carries same channel as NICAM A Two independent mono channels (NICAM A, NICAM B). FM1 carries same channel as NICAM A Data transmission only; no audio Unimplemented sound coding option (not yet defined by EBU NICAM 728 specification)
0 1 1
0 0 0
1 0 0
1 0 1
1
0
1
0
1 x
0 1
1 x
1 x
AUTO_FM: monitor bit for the AUTO_FM Status: 0: NICAM source is NICAM 1: NICAM source is FM
6.6.2. C_AD_BITS NICAM operation mode control bits and A[2...0] of the additional data bits. Format:
MSB 11 Auto _FM ... ... 7 A[2] C_AD_BITS 0023hex 6 A[1] 5 A[0] 4 C4 3 C3 2 C2 1 C1 LSB 0 S
6.6.3. ADD_BITS [10...3] 0038hex Contains the remaining 8 of the 11 additional data bits. The additional data bits are not yet defined by the NICAM 728 system. Format:
MSB 7 6 A[9] 5 A[8] ADD_BITS 0038hex 4 A[7] 3 A[6] 2 A[5] 1 A[4] LSB 0 A[3]
Important: "S" = Bit[0] indicates correct NICAM synchronization (S=1). If S=0, the MSP 3410D has not yet synchronized correctly to frame and sequence, or has lost synchronization. The remaining read registers are therefore not valid. The MSP 3410D mutes the NICAM output automatically and tries to synchronize again as long as MODE_REG[6] is set. The operation mode is coded by C4...C1 as shown in Table 6-14.
A[10]
6.6.4. CIB_BITS Cib bits 1 and 2 (see NICAM 728 specifications). Format:
MSB 7 x 6 x 5 x CIB_BITS 003Ehex 4 x 3 x 2 x 1 CIB1 LSB 0 CIB2
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PRELIMINARY DATA SHEET
MSP 34x0D
6.6.9. AGC_GAIN It is possible to read out the actual setting of AGC_GAIN in Automatic Gain Mode. In standard applications, this register is not of interest for the customer. AGC_GAIN max. amplification (20 dB) min. amplification (3 dB) 021Ehex 0001 0100 0000 0000 14hex 00hex
6.6.5. ERROR_RATE 0057hex Average error rate of the NICAM reception in a time interval of 182 ms, which should be close to 0. The initial and maximum value of ERROR_RATE is 2047. This value is also active, if the NICAM bit of MODE_REG is not set. Since the value is achieved by filtering, a certain transition time (appr. 0.5 sec) is unavoidable. Acceptable audio may have error_rates up to a value of 700dec. Individual evaluation of this value by the CCU and an appropriate threshold may define the fallback mode from NICAM to FM/AM-Mono in case of poor NICAM reception. The bit error rate per second (BER) can be calculated by means of the following formula: BER = ERROR_RATE x 12.3 x 10-6 /s If the automatic switching feature is applied (AUTO_FM; section 6.4.2. on page 24), reading of ERROR_RATE can be omitted.
6.7. Sequences to Transmit Parameters and to Start Processing After having been switched on, the MSP has to be initialized by transmitting the parameters according to the LOAD_SEQ_1/2 (see Table 6-15 on page 34). The data are immediately active after transmission into the MSP. It is no longer necessary to transmit LOAD_REG_1/2 or LOAD_REG_1 as it was for MSP 34x0B. Nevertheless, transmission of LOAD_REG_1/2 or LOAD_REG_1 does no harm. For NICAM operation, the following steps listed in `NICAM_WAIT, _READ, and _CHECK' in Table 6-15 must be taken. For FM-Stereo operation, the evaluation of the identification signal must be performed. For a positive identification check, the MSP 3410D sound channels have to be switched corresponding to the detected operation mode.
6.6.6. CONC_CT (for compatibility with MSP 3410B) This register contains the actual number of bit errors of the previous 728-bit data frame. Evaluation of CONC_CT is no longer recommended.
6.6.7. FAWCT_IST (for compatibility with MSP 3410B) For compatibility with MSP 3410B this value equals 12 as long as NICAM quality is sufficient. It decreases to 0 if NICAM reception gets poor. Evaluation of FAWCT_IST is no longer recommended.
6.6.8. PLL_CAPS It is possible to read out the actual setting of the PLL_CAPS. In standard applications, this register is not of interest for the customer. PLL_CAPS minimum frequency nominal frequency maximum frequency 021Fhex 0111 1111 0101 0110 RESET 0000 0000 7Fhex 56hex 00hex
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Table 6-15: Sequences to initialize and start the MSP 34x0D LOAD_SEQ_1/2: General Initialization General Programming Mode Write into MSP 34x0D: 1. AD_CV 2. FIR1 3. FIR2 4. MODE_REG 5. DCO1_LO 6. DCO1_HI 7. DCO2_LO 8. DCO2_HI AUDIO PROCESSING INIT
PRELIMINARY DATA SHEET
Demodulator Short Programming Write into MSP 34x0D: For example: Addr: 0020hex, Data 0008hex Alternatively, for terrestrial reception, the Autodetect feature can be applied.
Initialization of Audio Baseband Processing section, which may be customer-dependent (see section 7. on page 37). NICAM_WAIT: Automatic start of the NICAM Decoder if Bit[6] of MODE_REG is set to 1 1. Wait at least 0.25 s NICAM_CHECK: Read NICAM specific information and check for presence, operation mode, and quality of NICAM signal. Read out of MSP 3410D: 1. C_AD_BITS 2. CONC_CT or ERROR_RATE; if AUTO_FM is active, reading of CONC_CT or ERROR_RATE can be omitted. Evaluation of C_AD_BITS and CONC_CT or ERROR_RATE in the CCU (see section 6.6. on page 31). If necessary, switch the corresponding sound channels within the audio baseband processing section. FM_WAIT: Automatic start of the FM identification process if Bit[6] of MODE_REG is set to 0. 1. Ident Reset 2. Wait at least 0.5 s FM_IDENT_CHECK: Read FM specific information and check for presence, operation mode, and quality of dualcarrier FM. Read out of MSP 34x0D: 1. Stereo detection register (DSP register 0018hex, high part) Evaluation of the stereo detection register (see section 7.6.1. on page 50). If necessary, switch the corresponding sound channels within the audio baseband processing section. LOAD_SEQ_1: Reinitialization of Channel 1 without affecting Channel 2 Write into MSP 34x0D: 1. FIR1 2. MODE_REG 3. DCO1_LO 4. DCO1_HI (6 x 8 bit) (12 bit) (12 bit) Write into MSP 34x0D: For example: Addr: 0020hex, Data: 0003hex
PAUSE: Duration of "Pause" determines the repetition rate of the NICAM or the FM_IDENT check. Note: If downward-compatibility to the MSP 34x0B is required, the MSP 34x0D may be programmed according to the MSP 34x0B data sheet.
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PRELIMINARY DATA SHEET
MSP 34x0D
6.8.3. Multistandard Including System B/G with NICAM/FM-Mono and German DUAL-FM Fig. 6-3 shows a flow diagram for the CCU software, applied for the MSP 3410D in a TV set which supports all standards according to system B/G. For the instructions used in the diagram, please refer to Table 6-15. After having switched on the TV set and having initialized the MSP 3410D (LOAD_SEQ_1/2), FM-Mono sound is available. Fig. 6-3 shows that to check for any stereo or bilingual audio information, the TV sound standards 0008hex (B/G-NICAM) and 0003hex must simply be set alternately. If successful, the MSP 3410D must switch to the desired audio mode.
6.8. Software Proposals for Multistandard TV Sets To familiarize the reader with the programming scheme of the MSP 34x0D demodulator part, three examples in the shape of flow diagrams are shown in the following sections.
6.8.1. Multistandard Including System B/G with NICAM/FM-Mono only Fig. 6-1 shows a flow diagram for the CCU software, applied for the MSP 3410D in a TV set, which facilitates NICAM and FM-Mono sound. For the instructions, please refer to Table 6-15. If the program is changed, resulting in another program within the Scandinavian System B/G, no parameters of the MSP 3410D need be modified. To facilitate the check for NICAM, the CCU has only to continue at the 'NICAM_WAIT' instruction. During the NICAM identification process, the MSP 3410D must be switched to the FM-Mono sound.
START LOAD_SEQ_1/2 Set Sound Standard 0008hex
6.8.4. Satellite Mode Fig. 6-2 shows the simple flow diagram to be used for the MSP 34x0D in a satellite receiver. For FM-Mono operation, the corresponding FM carrier should preferably be processed at the MSP channel 2.
START MSP-Channel 1 FM2-Parameter MSP-Channel 2 FM1-Parameter
Audio Processing Init Audio Processing Init NICAM_WAIT STOP Pause NICAM_CHECK
Fig. 6-2: CCU software flow diagram: SAT mode
6.8.5. Automatic Search Function for FM Carrier Detection Fig. 6-1: CCU software flow diagram: standard B/G NICAM/FM-Mono only with Demodulator Short Programming Mode The AM demodulation ability of the MSP 34x0D offers the possibility to calculate the "field strength" of the momentarily selected FM carrier, which can be read out by the CCU. In SAT receivers, this feature can be used to make automatic FM carrier search possible. Therefore, the MSPD has to be switched to AM mode (MODE_REG[8]), FM prescale must be set to 7Fhex=+127dec, and the FM DC notch must be switched off. The sound IF frequency range must now be "scanned" in the MSPD channel 2 by means of the programmable quadrature mixer with an appropriate incremental frequency (i.e. 10 kHz).
6.8.2. Multistandard Including System I with NICAM/FM-Mono only This case is identical to the afore-mentioned. The only difference consists in selecting the UK TV sound standard, which is coded with 000Ahex of register 0020hex.
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PRELIMINARY DATA SHEET
START LOAD_SEQ_1/2 Set Sound Standard 0008hex
After each incrementation, a field strength value is available at the quasi-peak detector output (quasi-peak detector source must be set to FM), which must be examined for relative maxima by the CCU. This results in either continuing search or switching the MSP 34x0D back to FM demodulation mode. During the search process, the FIR2 must be loaded with the coefficient set "AUTOSEARCH", which enables small bandwidth, resulting in appropriate field strength characteristics. The absolute field strength value (can be read out of "quasi peak detector output FM1") also gives information on whether a main FM carrier or a subcarrier was detected, and as a practical consequence, the FM bandwidth (FIR1/2) and the deemphasis (50 s or adaptive) can be switched automatically. Due to the fact that a constant demodulation frequency offset of a few kHz, leads to a DC level in the demodulated signal, further fine tuning of the found carrier can be achieved by evaluating the "DC Level Readout FM1". Therefore, the FM DC Notch must be switched on, and the demodulator part must be switched back to FM demodulation mode. For a detailed description of the automatic search function, please refer to the corresponding MSP 34xxD Windows software. Note: The automatic search is still possible by evaluating only the DC Level Readout FM1 (DC Notch On) as it is described with the MSP 34x0B, but the above mentioned method is faster. If this DC Level method is applied with the MSP 34x0D, it is recommended to set MODE_REG[15] to 1 (AM gain = 12 dB) and to use the new Autosearch FIR2 coefficient set as given in Table 6-11.
Audio Processing Init
NICAM_WAIT
Pause Yes NICAM_CHECK NICAM ? No LOAD_SEQ_1 Set Sound Standard 0003hex
FM_WAIT
Pause FM_ IDENT_CHECK Mono LOAD_SEQ_1 Set Sound Standard 0008hex
Stereo/Biling.
Fig. 6-3: CCU software flow diagram: standard B/G with NICAM or FM-Stereo with Demodulator Short Programming
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PRELIMINARY DATA SHEET
MSP 34x0D
7. Programming the DSP Section (Audio Baseband Processing) 7.1. DSP Write Registers: Table and Addresses Table 7-1: DSP Write Registers; Subaddress: 12hex; if necessary, these registers are readable as well.
DSP Write Register Volume loudspeaker channel Volume / Mode loudspeaker channel Balance loudspeaker channel [L/R] Balance Mode loudspeaker Bass loudspeaker channel Treble loudspeaker channel Loudness loudspeaker channel Loudness Filter Characteristic Spatial effect strength loudspeaker ch. Spatial effect mode/customize Volume headphone channel Volume / Mode headphone channel Volume / SCART1 channel Volume / Mode SCART1 channel Loudspeaker channel source Loudspeaker channel matrix Headphone channel source Headphone channel matrix SCART1 channel source SCART1 channel matrix I2S channel source I2S channel matrix Quasi-peak detector source Quasi-peak detector matrix Prescale SCART Prescale FM/AM FM matrix Deemphasis FM Adaptive Deemphasis FM Prescale NICAM 0010hex 000Fhex 000Dhex 000Ehex 000Chex 000Bhex 000Ahex 0009hex 0008hex 0007hex 0006hex 0005hex 0002hex 0003hex 0004hex 0001hex Address 0000hex High/ Adjustable Range, Operational Modes Low H L H L H H H L H L H L H L H L H L H L H L H L H H L H L H [+12 dB ... -114 dB, MUTE] 1/8 dB Steps, Reduce Volume / Tone Control [0...100 / 100% and vv][-127 .. 0 / 0 dB and vv] [Linear mode / logarithmic mode] [+20 dB ... -12 dB] [+15 dB ... -12 dB] [0 dB ... +17 dB] [NORMAL, SUPER_BASS] [-100%...OFF...+100%] [SBE, SBE+PSE] [+12 dB ... -114 dB, MUTE] 1/8 dB Steps, Reduce Volume / Tone Control [00hex ... 7Fhex],[+12 dB ... -114 dB, MUTE] [Linear mode / logarithmic mode] [FM/AM, NICAM, SCART, I2S1, I2S2] [SOUNDA, SOUNDB, STEREO, MONO...] [FM/AM, NICAM, SCART, I2S1, I2S2] [SOUNDA, SOUNDB, STEREO, MONO...] [FM/AM, NICAM, SCART, I2S1, I2S2] [SOUNDA, SOUNDB, STEREO, MONO...] [FM/AM, NICAM, SCART, I2S1, I2S2] [SOUNDA, SOUNDB, STEREO, MONO...] [FM/AM, NICAM, SCART, I2S1, I2S2] [SOUNDA, SOUNDB, STEREO, MONO...] [00hex ... 7Fhex] [00hex ... 7Fhex] [NO_MAT, GSTEREO, KSTEREO] [50 s, 75 s, J17, OFF] [OFF, WP1] [00hex ... 7Fhex] Reset Mode MUTE 00hex 100% / 100% linear mode 0 dB 0 dB 0 dB NORMAL OFF SBE+PSE MUTE 00hex 00hex linear mode FM/AM SOUNDA FM/AM SOUNDA FM/AM SOUNDA FM/AM SOUNDA FM/AM SOUNDA 00hex 00hex NO_MAT 50 s OFF 00hex
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PRELIMINARY DATA SHEET
Table 7-1: DSP Write Registers; Subaddress: 12hex; if necessary, these registers are readable as well., continued
DSP Write Register Prescale I2S2 ACB Register (SCART Switching Facilities and Digital Control Output Pins) Beeper Identification Mode Prescale I2S1 FM DC Notch Mode Tone Control Equalizer loudspeaker ch. band 1 Equalizer loudspeaker ch. band 2 Equalizer loudspeaker ch. band 3 Equalizer loudspeaker ch. band 4 Equalizer loudspeaker ch. band 5 Automatic Volume Correction Volume Subwoofer channel Subwoofer Channel Corner Frequency Subwoofer: Complementary High-pass Balance headphone channel [L/R] Balance Mode headphone Bass headphone channel Treble headphone channel Loudness headphone channel Loudness filter characteristic Volume SCART2 channel Volume / Mode SCART2 channel SCART2 channel source SCART2 channel matrix 0041hex 0040hex 0031hex 0032hex 0033hex 0030hex Address 0012hex 0013hex High/ Adjustable Range, Operational Modes Low H H/L [00hex ... 7Fhex] Bits [15...0] Reset Mode 10hex 00hex
0014hex 0015hex 0016hex 0017hex 0020hex 0021hex 0022hex 0023hex 0024hex 0025hex 0029hex 002Chex 002Dhex
H/L L H L H H H H H H H H H L H L H H H L H L H L
[00hex ... 7Fhex]/[00hex ... 7Fhex] [B/G, M] [00hex ... 7Fhex] [ON, OFF] [BASS/TREBLE, EQUALIZER] [+12 dB ... -12 dB] [+12 dB ... -12 dB] [+12 dB ... -12 dB] [+12 dB ... -12 dB] [+12 dB ... -12 dB] [off, on, decay time] [0 dB ... -30 dB, mute] [50 Hz ... 400 Hz] [off, on] [0...100 / 100% and vv][-127...0 / 0 dB and vv] [Linear mode / logarithmic mode] [+20 dB ... -12 dB] [+15 dB ... -12 dB] [0 dB ... +17 dB] [NORMAL, SUPER_BASS] [00hex ... 7Fhex],[+12 dB ... -114 dB, MUTE] [Linear mode / logarithmic mode] [FM, NICAM, SCART, I2S1, I2S2] [SOUNDA, SOUNDB, STEREO, MONO...]
0/0 B/G 10hex ON BASS/TREB 0 dB 0 dB 0 dB 0 dB 0 dB off 0 dB 00hex off 100% /100% linear mode 0 dB 0 dB 0 dB NORMAL 00hex linear mode FM SOUNDA
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PRELIMINARY DATA SHEET
MSP 34x0D
7.2. DSP Read Registers: Table and Addresses Table 7-2: DSP Read Registers; Subaddress: 13hex; these registers are not writable. DSP Read Register Stereo detection register Quasi-peak readout left Quasi-peak readout right DC level readout FM1/Ch2-L DC level readout FM2/Ch1-R MSP hardware version code MSP major revision code MSP product code MSP ROM version code 001Fhex Address 0018hex 0019hex 001Ahex 001Bhex 001Chex 001Ehex High/Low H H&L H&L H&L H&L H L H L Output Range [80hex ... 7Fhex] [0000hex ... 7FFFhex] [0000hex ... 7FFFhex] [8000hex ... 7FFFhex] [8000hex ... 7FFFhex] [00hex ... FFhex] [00hex ... FFhex] [00hex ... 0Ahex] [00hex ... FFhex] 8 bit two's complement 16 bit two's complement 16 bit two's complement 16 bit two's complement 16 bit two's complement
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7.3. DSP Write Registers: Functions and Values Write registers are 16 bit wide, whereby the MSB is denoted bit [15]. Transmissions via I2C bus have to take place in 16-bit words. Some of the defined 16-bit words are divided into low [7...0] and high [15...8] byte, or in an other manner, thus holding two different control entities. All write registers are readable. Unused parts of the 16-bit registers must be zero. Addresses not given in this table must not be written at any time!
PRELIMINARY DATA SHEET
With Fast Mute, volume is reduced to mute position by digital volume only. Analog volume is not changed. This reduces any audible DC plops. Going back from Fast Mute should be done to the volume step which was in existence before Fast Mute was activated. The Fast Mute facility is activated by the I2C command. After 75 ms (typically), the signal is completely ramped down.
7.3.1. Volume - Loudspeaker and Headphone Channel Volume Loudspeaker Volume Headphone +12 dB +11.875 dB +0.125 dB 0 dB 0000hex 0006hex [15...4] [15...4]
Clipping Mode Loudspeaker Clipping Mode Headphone Reduce Volume Reduce Tone Control
0000hex 0006hex 0000 RESET 0001 0010
[3..0] [3..0] 0hex 1hex 2hex
0111 1111 00001) 7F0hex 0111 1110 1110 0111 0011 0010 0111 0011 0000 0111 0010 1110 0000 0001 0010 0000 0001 0000 0000 0000 0000 RESET 1111 1111 1110 7EEhex 732hex 730hex 72Ehex 012hex 010hex 000hex FFEhex
Compromise Mode
-0.125 dB -113.875 dB -114 dB
Mute Fast Mute
1)
If the clipping mode is set to "Reduce Volume", the following clipping procedure is used: To prevent severe clipping effects with bass, treble, or equalizer boosts, the internal volume is automatically limited to a level where, in combination with either bass, treble, or equalizer setting, the amplification does not exceed 12 dB. If the clipping mode is "Reduce Tone Control", the bass or treble value is reduced if amplification exceeds 12 dB. If the equalizer is switched on, the gain of those bands is reduced, where amplification together with volume exceeds 12 dB. If the clipping mode is "Compromise Mode", the bass or treble value and volume are reduced half and half if amplification exceeds 12 dB. If the equalizer is switched on, the gain of those bands is reduced half and half, where amplification together with volume exceeds 12 dB.
Bit[4] must always be set to 0
The highest given positive 12-bit number (7F0hex) yields in a maximum possible gain of 12 dB. Decreasing the volume register by 2 LSBs decreases the volume by 0.125 dB. Volume settings lower than the given minimum mute the output. With large scale input signals, positive volume settings may lead to signal clipping. The MSPD loudspeaker and headphone volume function is divided up into a digital and an analog section.
Example: Red. Volume Red. Tone Con. Compromise
Vol.: +6 dB 3 6 4.5
Bass: +9 dB 9 6 7.5
Treble: +5 dB 5 5 5
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MSP 34x0D
7.3.2. Balance - Loudspeaker and Headphone Channel Positive balance settings reduce the left channel without affecting the right channel; negative settings reduce the right channel leaving the left channel unaffected. In linear mode, a step by 1 LSB decreases or increases the balance by about 0.8 % (exact figure: 100/127). In logarithmic mode, a step by 1 LSB decreases or increases the balance by 1 dB.
Logarithmic Mode Balance Loudspeaker Channel [L/R] Balance Headphone Channel [L/R] Left -127 dB, Right 0 dB Left -126 dB, Right 0 dB Left -1 dB, Right 0 dB Left 0 dB, Right 0 dB 0001hex 0030hex 0111 1111 0111 1110 0000 0001 0000 0000 RESET 1111 1111 1000 0001 1000 0000 H H 7Fhex 7Ehex 01hex 00hex FFhex 81hex 80hex
Balance Mode Loudspeaker Balance Mode Headphone linear logarithmic
0001hex 0030hex 0000 RESET 0001
[3..0] [3..0]
Left 0 dB, Right -1 dB 0hex 1hex Left 0 dB, Right -127 dB Left 0 dB, Right -128 dB
Linear Mode Balance Loudspeaker Channel [L/R] Balance Headphone Channel [L/R] Left muted, Right 100 % Left 0.8 %, Right 100 % Left 99.2 %, Right 100 % Left 100 %, Right 100 % Left 100 %, Right 99.2 % Left 100 %, Right 0.8 % Left 100 %, Right muted 0001hex 0030hex 0111 1111 0111 1110 0000 0001 0000 0000 RESET 1111 1111 1000 0010 1000 0001 H H
7.3.3. Bass - Loudspeaker and Headphone Channel Bass Loudspeaker Bass Headphone +20 dB 7Fhex 7Ehex 01hex 00hex FFhex 82hex 81hex +18 dB +16 dB +14 dB +12 dB +11 dB +1 dB +1/8 dB 0 dB 0002hex 0031hex 0111 1111 0111 1000 0111 0000 0110 1000 0110 0000 0101 1000 0000 1000 0000 0001 0000 0000 RESET 1111 1111 1111 1000 1010 1000 1010 0000 H H 7Fhex 78hex 70hex 68hex 60hex 58hex 08hex 01hex 00hex FFhex F8hex A8hex A0hex
-1/8 dB -1 dB -11 dB -12 dB
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With positive bass settings, internal overflow may occur even with overall volume less than 0 dB. This will lead to a clipped output signal. Therefore, it is not recommended to set bass to a value that, in conjunction with volume, would result in an overall positive gain. Loudspeaker channel: Bass and Equalizer cannot work simultaneously (see section 7.3.22.: Mode Tone Control). If Equalizer is used, Bass and Treble coefficients must be set to zero and vice versa.
PRELIMINARY DATA SHEET
7.3.5. Loudness - Loudspeaker and Headphone Channel Loudness Loudspeaker Loudness Headphone +17 dB +16 dB 0004hex 0033hex 0100 0100 0100 0000 0000 0100 0000 0000 RESET H H 44hex 40hex 04hex 00hex
7.3.4. Treble - Loudspeaker and Headphone Channel Treble Loudspeaker Treble Headphone +15 dB +14 dB +1 dB +1/8 dB 0 dB 0003hex 0032hex 0111 1000 0111 0000 0000 1000 0000 0001 0000 0000 RESET 1111 1111 1111 1000 1010 1000 1010 0000 H H 78hex 70hex 08hex 01hex 00hex FFhex F8hex A8hex A0hex
+1 dB 0 dB
Mode Loudness Loudspeaker Mode Loudness Headphone Normal (constant volume at 1 kHz) Super Bass (constant volume at 2 kHz)
0004hex 0033hex 0000 0000 RESET 0000 0100
L L 00hex 04hex
-1/8 dB -1 dB -11 dB -12 dB
With positive treble settings, internal overflow may occur even with overall volume less than 0 dB. This will lead to a clipped output signal. Therefore, it is not recommended to set treble to a value that, in conjunction with volume, would result in an overall positive gain. Loudspeaker channel: Treble and Equalizer cannot work simultaneously (see section 7.3.22.: Mode Tone Control). If Equalizer is used, Bass and Treble coefficients must be set to zero and vice versa.
Loudness increases the volume of low and high frequency signals, while keeping the amplitude of the 1 kHz reference frequency constant. The intended loudness has to be set according to the actual volume setting. Because loudness introduces gain, it is not recommended to set loudness to a value that, in conjunction with volume, would result in an overall positive gain. By means of `Mode Loudness', the corner frequency for bass amplification can be set to two different values. In Super Bass mode, the corner frequency is shifted up. The point of constant volume is shifted from 1 kHz to 2 kHz.
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PRELIMINARY DATA SHEET
MSP 34x0D
There are several spatial effect modes available: Mode A (low byte = 00hex) is compatible to the formerly used spatial effect. Here, the kind of spatial effect depends on the source mode. If the incoming signal is in mono mode, Pseudo Stereo Effect is active; for stereo signals, Pseudo Stereo Effect and Stereo Basewidth Enlargement is active. The strength of the effect is controllable by the upper byte. A negative value reduces the stereo image. A rather strong spatial effect is recommended for small TV sets where loudspeaker spacing is rather close. For large screen TV sets, a more moderate spatial effect is recommended. In mode A, even in case of stereo input signals, Pseudo Stereo Effect is active, which reduces the center image. In Mode B, only Stereo Basewidth Enlargement is effective. For mono input signals, the Pseudo Stereo Effect has to be switched on. It is worth mentioning, that all spatial effects affect amplitude and phase response. With the lower 4 bits, the frequency response can be customized. A value of 0000bin yields a flat response for center signals (L = R) but a high pass function of L or R only signals. A value of 0110bin has a flat response for L or R only signals but a low-pass function for center signals. By using 1000bin, the frequency response is automatically adapted to the sound material by choosing an optimal high-pass gain.
7.3.6. Spatial Effects - Loudspeaker Channel Spatial Effect Strength Loudspeaker Enlargement 100% Enlargement 50% Enlargement 1.5% Effect off Reduction 1.5% Reduction 50% Reduction 100% 0005hex 0111 1111 0011 1111 0000 0001 0000 0000 RESET 1111 1111 1100 0000 1000 0000 H 7Fhex 3Fhex 01hex 00hex FFhex C0hex 80hex
Spatial Effect Mode Loudspeaker Stereo Basewidth Enlargement (SBE) and Pseudo Stereo Effect (PSE). (Mode A) Stereo Basewidth Enlargement (SBE) only. (Mode B)
0005hex 0000 RESET
[7...4] 0hex
0010
2hex
Spatial Effect Customize Coefficient Loudspeaker max. high-pass gain 2/3 high-pass gain 1/3 high-pass gain min. high-pass gain automatic
0005hex
[3...0]
0000 RESET 0010 0100 0110 1000
0hex 2hex 4hex 6hex 8hex
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MSP 34x0D
7.3.7. Volume - SCART1 and SCART2 Channel Volume Mode SCART1 Volume Mode SCART2 linear logarithmic 0007hex 0040hex 0000 RESET 0001 [3...0] [3...0] 0hex 1hex
PRELIMINARY DATA SHEET
7.3.8. Channel Source Modes Loudspeaker Source Headphone Source SCART1 Source SCART2 Source I2S Source Quasi-Peak Detector Source 0008hex 0009hex 000Ahex 0041hex 000Bhex 000Chex 0000 0000 RESET 0000 0001 0000 0011 0000 0100 0000 0010 0000 0101 0000 0110 H H H H H H 00hex 01hex 03hex 04hex 02hex 05hex 06hex
Linear Mode Volume SCART1 Volume SCART2 OFF 0 dB gain (digital full scale (FS) to 2 VRMS output) +6 dB gain (-6 dBFS to 2 VRMS output) 0007hex 0040hex 0000 0000 RESET 0100 0000 H H 00hex 40hex
FM/AM NICAM none (MSPB/C: SBUS12) none (MSPB/C: SBUS34) SCART I2S1 0111 1111 7Fhex I2S2
Logarithmic Mode Volume SCART1 Volume SCART2 +12 dB +11.875 dB +0.125 dB 0 dB 0007hex 0040hex 0111 1111 0000 0111 1110 1110 0111 0011 0010 0111 0011 0000 0111 0010 1110 0000 0001 0010 0000 0001 0000 0000 0000 0000 RESET [15...4] [15...4] 7F0hex 7EEhex 732hex 730hex 72Ehex 012hex 010hex 000hex
-0.125 dB -113.875 dB -114 dB
Mute
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Micronas
PRELIMINARY DATA SHEET
MSP 34x0D
7.3.10. SCART Prescale L L OFF L L L L 00hex 10hex 20hex 30hex 40hex 50hex 60hex 70hex 80hex 90hex 0 dB gain (2 VRMS input to digital full scale) +14 dB gain (400 mVRMS input to digital full scale) 0000 0000 RESET 0001 1001 0111 1111 00hex 19hex 7Fhex Volume Prescale SCART 000Dhex H
7.3.9. Channel Matrix Modes Loudspeaker Matrix Headphone Matrix SCART1 Matrix SCART2 Matrix I2S Matrix Quasi-Peak Detector Matrix SOUNDA / LEFT / MSP-IF-CHANNEL2 SOUNDB / RIGHT / MSP-IF-CHANNEL1 STEREO MONO SUM / DIFF AB_XCHANGE PHASE_CHANGE_B PHASE_CHANGE_A A_ONLY B_ONLY 0008hex 0009hex 000Ahex 0041hex 000Bhex 000Chex 0000 0000 RESET 0001 0000 0010 0000 0011 0000 0100 0000 0101 0000 0110 0000 0111 0000 1000 0000 1001 0000
The sum/difference mode can be used together with the quasi-peak detector to determine the sound material mode. If the difference signal on channel B (right) is near to zero, and the sum signal on channel A (left) is high, the incoming audio signal is mono. If there is a significant level on the difference signal, the incoming audio is stereo.
Micronas
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MSP 34x0D
7.3.11. FM/AM Prescale Volume Prescale FM (Normal FM Mode) OFF Maximum Volume (28 kHz deviation 1) recommended FIRbandwidth: 130 kHz) Deviation 50 kHz1) recommended FIRbandwidth: 200 kHz Deviation 75 kHz1) recommended FIRbandwidth: 200 or 280 kHz Deviation 150 kHz1) recommended FIRbandwidth: 380 kHz Maximum deviation 192 kHz1) recommended FIRbandwidth: 380 kHz Prescale for adaptive deemphasis WP1 recommended FIRbandwidth: 130 kHz Volume Prescale FM (High Deviation Mode) OFF Deviation 150 kHz1) recommended FIRbandwidth: 380 kHz Maximum deviation 384 kHz1) recommended FIRbandwidth: 500 kHz Volume Prescale AM OFF SIF input level: 0.1 Vpp - 0.8 Vpp 1) 2) 0.8 Vpp - 1.4 Vpp 1) 0111 1100 7Chex <7Chex 000Ehex 0000 0000 RESET 0111 1111 H 00hex 7Fhex
PRELIMINARY DATA SHEET
For the High Deviation Mode, the FM prescaling values can be used in the range from 14hex to 30hex. Please consider the internal reduction of 6 dB for this mode. The FIR-bandwidth should be selected to 500 kHz.
1)
Given deviations will result in internal digital fullscale signals. Appropriate clipping headroom has to be set by the customer. This can be done by decreasing the listed values by a specific factor. In the mentioned SIF-level range, the AM-output level remains stable and independent of the actual SIF-level. In this case, only the AM degree of audio signals above 40 Hz determines the AM-output level.
2)
0100 1000
48hex
0011 0000
30hex
7.3.12. FM Matrix Modes (see also Table 4-1) FM Matrix 000Ehex 0000 0000 RESET 0000 0001 0000 0010 L 00hex 01hex 02hex
0001 1000
18hex
NO MATRIX GSTEREO
0001 0011
13hex
KSTEREO
0001 0000
10hex
NO_MATRIX is used for terrestrial mono or satellite stereo sound. GSTEREO dematrixes [(L+R)/2, R] to [L, R] and is used for German dual carrier stereo system (Standard B/G). KSTEREO dematrixes [(L+R)/2, (L-R)/2] to [L, R] and is used for the Korean dual carrier stereo system (Standard M).
000Ehex 0000 0000 RESET 0011 0000
H 7.3.13. FM Fixed Deemphasis 00hex 30hex Deemphasis FM 50 s 75 s 000Fhex 0000 0000 RESET 0000 0001 0000 0100 0011 1111 H 00hex 01hex 04hex 3Fhex
0001 0100
14hex
J17 OFF
000Ehex 0000 0000 RESET
H 00hex 7.3.14. FM Adaptive Deemphasis FM Adaptive Deemphasis WP1 OFF WP1 000Fhex 0000 0000 RESET 0011 1111 L 00hex 3Fhex
Note: For AM, the bit MODE_REG[15] must be 1
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PRELIMINARY DATA SHEET
MSP 34x0D
Definition of SCART Switching Facilities (see Fig. 4-3 on page 13)
7.3.15. NICAM Prescale Volume Prescale NICAM OFF 0010hex 0000 0000 RESET 0 dB gain +12 dB gain 0010 0000 0111 1111 20hex 7Fhex H
ACB Register 00hex DSP IN Selection of Source: * SC1_IN_L/R MONO_IN SC2_IN_L/R SC3_IN_L/R SC4_IN_L/R Mute SC1_OUT_L/R Selection of Source: * SC3_IN_L/R SC2_IN_L/R MONO_IN SCART1_L/R via D/A SCART2_L/R via D/A SC1_IN_L/R SC4_IN_L/R Mute SC2_OUT_L/R Selection of Source: * SCART1_L/R via D/A SC1_IN_L/R MONO_IN SCART2_L/R via D/A SC2_IN_L/R SC3_IN_L/R SC4_IN_L/R Mute
0013hex
[13...0]
xx xx xx xx xx xx
xx00 xx01 xx10 xx11 xx00 xx11
xx00 xx00 xx00 xx00 xx10 xx10
0000 0000 0000 0000 0000 0000
7.3.16. NICAM Deemphasis A J17 Deemphasis is always applied to the NICAM signal. It is not switchable. 7.3.17. I2S1 and I2S2 Prescale Prescale I2S1 Prescale I2S2 OFF 0 dB gain +18 dB gain 0016hex 0012hex 0000 0000 0001 0000 RESET 0111 1111 H H 00hex 10hex 7Fhex
xx xx xx xx xx xx xx xx
00xx 01xx 10xx 11xx 00xx 01xx 10xx 11xx
x0x0 x0x0 x0x0 x0x0 x1x0 x1x0 x1x0 x1x0
0000 0000 0000 0000 0000 0000 0000 0000
7.3.18. ACB Register Definition of Digital Control Output Pins ACB Register D_CTR_OUT0 low (RESET) high D_CTR_OUT1 low (RESET) high 0013hex x0 x1 0x 1x [15..14]
00 01 10 00 01 10 11 11
xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
0xx0 0xx0 0xx0 1xx0 1xx0 1xx0 1xx0 0xx0
0000 0000 0000 0000 0000 0000 0000 0000
* = RESET position, which becomes active at the time of the first write transmission on the control bus to the audio processing part (DSP). By writing to the ACB register first, the RESET state can be redefined. Note: If "MONO_IN" is selected at the DSP_IN selection, the channel matrix mode of the corresponding output channel(s) must be set to "sound A".
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MSP 34x0D
7.3.19. Beeper Beeper Volume OFF Maximum Volume (full digital scale FDS) Beeper Frequency 16 Hz (lowest) 1 kHz 4 kHz (highest) 0014hex 0000 0000 RESET 0111 1111 0014hex 0000 0001 0100 0000 1111 1111 H 00hex 7Fhex FM DC Notch L 01hex 40hex FFhex OFF ON 7.3.21. FM DC Notch
PRELIMINARY DATA SHEET
The DC compensation filter (FM DC Notch) for FM input can be switched off. This is used to speed up the automatic search function (see section 6.8.5. on page 35). In normal FM mode, the FM DC Notch should be switched on. 0017hex 0000 0000 Reset 0011 1111 L 00hex 3Fhex
7.3.22. Mode Tone Control A square wave beeper can be added to the loudspeaker channel and the headphone channel. The addition point is just before loudness and volume adjustment. Mode Tone Control Bass and Treble Equalizer 0020hex 0000 0000 RESET 1111 1111 H 00hex FFhex
7.3.20. Identification Mode Identification Mode Standard B/G (German Stereo) Standard M (Korean Stereo) Reset of Ident-Filter 0015hex 0000 0000 RESET 0000 0001 0011 1111 L 00hex
By means of `Mode Tone Control', Bass/Treble or Equalizer may be activated.
7.3.23. Automatic Volume Correction (AVC) 01hex AVC 3Fhex AVC AVC AVC 8 sec. 4 sec. 2 sec. 20 ms On/Off off and Reset of int. variables on Decay Time (long) (middle) (short) (very short) 0029hex 0000 RESET 1000 0029hex 1000 0100 0010 0001 [15...12] 0hex 8hex [11...8] 8hex 4hex 2hex 1hex
To shorten the response time of the identification algorithm after a program change between two FM-Stereo capable programs, the reset of the ident-filter can be applied. Sequence: 1. Program change 2. Reset ident-filter 3. Set identification mode back to standard B/G or M 4. Read stereo detection register
Different sound sources (e.g. terrestrial channels, SAT channels, or SCART) fairly often do not have the same volume level. Advertisement during movies, as well, usually has a different (higher) volume level than the movie itself. The Automatic Volume Correction (AVC) solves this problem and equalizes the volume levels.
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PRELIMINARY DATA SHEET
MSP 34x0D
7.3.24. Subwoofer Channel The subwoofer channel is created by combining the left and right channels directly behind the tone control filter block. A third order low-pass filter with programmable corner frequency and volume adjustment according to the main channel output is performed to the bass signal. Additionally, at the loudspeaker channels, a complementary high-pass filter can be switched on.
The absolute value of the incoming signal is fed into a filter with 16 ms attack time and selectable decay time. The decay time must be adjusted as shown in the table above. This attack/decay filter block works similar to a peak hold function. The volume correction value with its quasi continuous step width is calculated using the attack/decay filter output. The Automatic Volume Correction functions with an internal reference level of -18 dBr. This means that input signals with a volume level of -18 dBr will not be affected by the AVC. If the input signals vary in a range of -24 dB to 0 dB, the AVC maintains a fixed output level of -18 dBr. Fig. 7-1 shows the AVC output level versus its input level. For prescale and volume registers set to 0 dB, a level of 0 dBr corresponds to full scale input / output. This is - SCART in-, output 0 dBr = 2.0 Vrms - Loudspeaker and Aux output 0 dBr = 1.4 Vrms
Subwoofer Channel Volume Adjust 0 dB
002Chex 0000 0000 RESET 1111 1111 1110 0011 1110 0010 1000 0000 002Dhex RESET 0000 0101 0010 1000 002Dhex 0000 0000 RESET 0000 0001
H 00hex FFhex E3hex E2hex 80hex H 00hex 05hex 28hex L 00hex 01hex
-1 dB -29 dB -30 dB
Mute
output level [dBr]
-12 -18 -24
Subwoofer Channel Corner Frequency 50 Hz ... 400 Hz e.g. 50 Hz = 5dec 400 Hz = 40dec Subwoofer: Complementary High-pass HP off
-30
-24
-18
-12
-6
0
+6
input level [dBr] Fig. 7-1: Simplified AVC characteristics
HP on
To reset the internal variables, the AVC should be switched off and on during any channel or source change. For standard applications, the recommended decay time is 4 sec. Note: AVC should not be used in any Dolby Pro Logic mode, except PANORAMA, where no other than the loudspeaker output is active.
Micronas
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MSP 34x0D
7.3.25. Equalizer Loudspeaker Channel Band 1 (below 120 Hz) Band 2 (Center: 500 Hz) Band 3 (Center: 1.5 kHz) Band 4 (Center: 5 kHz) Band 5 (above 10 kHz) +12 dB +11 dB +1 dB +1/8 dB 0 dB 0021hex 0022hex 0023hex 0024hex 0025hex 0110 0000 0101 1000 0000 1000 0000 0001 0000 0000 RESET 1111 1111 1111 1000 1010 1000 1010 0000 H H H H H 60hex 58hex 08hex 01hex 00hex FFhex F8hex A8hex A0hex
Mono SCART1...3
PRELIMINARY DATA SHEET
7.5. Phase Relationship of Analog Outputs The analog output signals: Loudspeaker, headphone, and SCART2 all have the same phases. The user does not need to change output phases when using these analog outputs directly. The SCART1 output has opposite phase. Using the I2S-outputs for other DSPs or D/A converters, care must be taken to adjust for the correct phase. If the attached coprocessor is one of the MSP family, the following schematics help to determine the phase relationship.
I2S_in I2S_out
Loudspeaker Headphone Audio Baseband Processing SCART2 SCART1
-1/8 dB -1 dB -11dB -12 dB
SCART1...2
With positive equalizer settings, internal overflow may occur even with overall volume less than 0 dB. This will lead to a clipped output signal. Therefore, it is not recommended to set equalizer bands to a value that, in conjunction with volume, would result in an overall positive gain. Equalizer must not be used simultaneously with Bass and Treble (Mode Tone Control must be set to FF to use the Equalizer). If Bass and Treble are used, Equalizer coefficients must be set to zero.
Fig. 7-2: Phase diagram of the MSP 34x0D
7.6. DSP Read Registers: Functions and Values All readable registers are 16-bit wide. Transmissions via I2C bus have to take place in 16-bit words. Single data entries are 8 bit. Some of the defined 16-bit words are divided into low and high byte, thus holding two different control entities. These registers are not writable.
7.4. Exclusions for the Audio Baseband Features In general, all functions can be switched independently of the others. Exceptions: 1. NICAM cannot be processed simultaneously with the FM2 channel. 2. FM adaptive deemphasis WPI cannot be processed simultaneously with the FM-identification. 7.6.1. Stereo Detection Register Stereo Detection Register Stereo Mode MONO STEREO BILINGUAL 0018hex H
Reading (two's complement) near zero positive value (ideal reception: 7Fhex) negative value (ideal reception: 80hex)
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PRELIMINARY DATA SHEET
MSP 34x0D
7.6.5. MSP Major Revision Code
7.6.2. Quasi-Peak Detector Quasi-Peak Readout Left Quasi-Peak Readout Right Quasi peak readout 0019hex 001Ahex H+L H+L
Major Revision MSP 34x0D
001Ehex 04hex
L
[0000hex ... 7FFFhex] values are 16 bit two's complement
The MSP 34x0D is the fourth generation of ICs in the MSP family.
7.6.6. MSP Product Code The quasi peak readout register can be used to read out the quasi peak level of any input source, in order to adjust all inputs to the same normal listening level. The refresh rate is 32 kHz. The feature is based on the filter time constants: attack time: 1.3 ms decay time: 37 ms Product MSP 3400D MSP 3410D 001Fhex 0000 0000 0000 1010 H 00hex 0Ahex
By means of the MSP product code, the control processor is able to decide whether or not NICAM-controlling should be accomplished.
7.6.3. DC Level Register DC Level Readout FM1 (MSP-Ch2) DC Level Readout FM2 (MSP-Ch1) DC Level 001Bhex 001Chex H+L H+L 7.6.7. MSP ROM Version Code ROM Version Major software revision [8000hex ... 7FFFhex] values are 16 bit two's complement MSP 34x0D - B4 001Fhex [00hex ... FFhex] 0010 0100 24hex L
The DC level register measures the DC component of the incoming FM signals (FM1 and FM2). This can be used for seek functions in satellite receivers and for IF FM frequencies fine tuning. A too low demodulation frequency (DCO) results in a positive DC-level and vice-versa. For further processing, the DC content of the demodulated FM signals is suppressed. The time constant , defining the transition time of the DC Level Register, is approximately 28 ms.
A change in the ROM version code defines internal software optimizations, that may have influence on the chip's behavior, e.g. new features may have been included. While a software change is intended to create no compatibility problems, customers that would like to use the new functions, can identify new MSP 34x0D versions according to this number. To avoid compatibility problems with MSP 34x0B, an offset of 20hex is added to the ROM version code of the chip's imprint.
7.6.4. MSP Hardware Version Code Hardware Version Hardware Version MSP 34x0D - B4 001Ehex [00hex ... FFhex] 02hex H
A change in the hardware version code defines hardware optimizations that may have influence on the chip's behavior. The readout of this register is identical to the hardware version code in the chip's imprint.
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MSP 34x0D
8. Differences between MSP 3400C, MSP 3400D, MSP 3410B, and MSP 3410D
Feature Hardware NICAM S-Bus Output S-Bus Input Second I2S Data Input ADR Interface No No S_DA_IN I2S_DA_IN2 ADR_CL, ADR_WS, ADR_DA No No No No I2S_DA_IN2 ADR_CL, ADR_WS, ADR_DA Yes MSP 3400C MSP 3400D-B4
PRELIMINARY DATA SHEET
MSP 3410B-F7
MSP 3410D-B4
Yes S_DA_OUT S_DA_IN No No
Yes No No I2S_DA_IN2 ADR_CL, ADR_WS, ADR_DA Yes
Second SCART D/A Converter Demodulator Demodulator Short Programming Autodetection for terr. TV Sound Standards Automatic switching from NICAM to FM and vv. ADCV[10] ADCV[11] MODE_REG[1]: MODE_REG[2]: MODE_REG[6]: MODE_REG[7]: MODE_REG[10]: MODE_REG[11]: MODE_REG[12]: MODE_REG[13]: MODE_REG[14] Carrier Mute Level Carrier Mute Level Tri-state digital outputs Tri-state digital outputs I2S outputs NICAM FM1FM2 S-Bus Setting S-Bus Mode 6 dB gain in MSP-Ch1 FIR filter coeff. set for MSP-Ch1 Mode of ADR Interface
No
No No No Carrier Mute Level Carrier Mute Level 0: active 1: tri-state 0: active 1: tri-state no function no function no function no function 0: on 1: off 0: use FIR1 1: use FIR2 0: normal mode 1: ADR/SaRa
Yes Yes Yes not used not used 0: active 1: tri-state 0: active 1: tri-state no function no function no function no function 0: on 1: off 0: use FIR1 1: use FIR2 0: normal mode 1: ADR/SaRa
No No No FIFO Watchdog On/Off not used enable Pay-TV disable NICAM Descrambler 0: FM 1: NICAM 0: NICAM 1: FM NICAM/FM on S-Bus Mode of internal S-Bus always on always FIR1 No
Yes Yes Yes not used not used 0: active 1: tri-state 0: active 1: tri-state 0: FM 1: NICAM no function no function no function 0: on 1: off 0: use FIR1 1: use FIR2 0: normal mode 1: ADR/SaRa
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PRELIMINARY DATA SHEET
MSP 34x0D
Feature Demodulator MODE_REG[15]: FAWCT_SOLL Gain for AM-Demodulation (DEMOD W Addr. 107hex)
MSP 3400C
MSP 3400D-B4
MSP 3410B-F7
MSP 3410D-B4
0: 0 dB1) 1: 12 dB Not necessary Not necessary Not necessary Not necessary Not necessary No No
0: 0 dB 1: 12 dB Not necessary Not necessary Not necessary Not necessary Not necessary Not necessary not compatible, not for customer use, No No No I2C Addr. 021Ehex I2C Addr. 021Fhex
No Yes Yes Yes Yes Yes Yes values as described in Mubi-Software Yes Yes No not possible not possible
0: 0 dB 1: 12 dB Not necessary Not necessary Not necessary Not necessary Not necessary Not necessary not compatible, not for customer use, Yes, but not necessary Yes, but not recommended Yes I2C Addr. 021Ehex I2C Addr. 021Fhex
FAWCT_ER_TOL (DEMOD W Addr. 10Fhex) AUDIO_PLL LOAD_REG_1/2 LOAD_REG_1 (DEMOD W Addr. 2D7hex) (DEMOD W Addr. 56hex) (DEMOD W Addr. 60hex)
SEARCH_NICAM (DEMOD W Addr. 78hex) SELF_TEST (DEMOD W Addr. 792hex)
FAWCT_IST CONC_CT ERROR_RATE
(DEMOD R Addr. 25hex) (DEMOD R Addr. 58hex) (DEMOD R Addr. 57hex)
No No No I2C Addr. 001Ehex I2C Addr. 001Fhex
Reading out RMS value of AGC Reading out internal PLL capacitance switches Audio Baseband Processing Improved oversampling filters for all D/A converters Mode Loudness Loudspeaker channel (DSP W Addr. 0004hex L) Spatial Effect Loudspeaker (DSP W Addr. 05hex L) Prescale I2S2 Prescale I2S1 (DSP W Addr. 0012hex H) (DSP W Addr. 0016hex H)
Yes 00hex: normal 04hex: Super Bass Mode/ Customize Yes1) Yes1) Yes 00hex: Bass/ Treble FFhex:Equalizer [+12 ...-12 dB] Yes1)
Yes 00hex: normal 04hex: Super Bass Mode/ Customize Yes Yes Yes 00hex: Bass/ Treble FFhex:Equalizer [+12 ...-12 dB] Yes
No 00hex: normal 04hex: Super Version F7 always 0 No No No always Bass/ Treble not implemented No
Yes 00hex: normal 04hex: Super Bass Mode/ Customize Yes Yes Yes 00hex: Bass/ Treble FFhex:Equalizer [+12 ...-12 dB] Yes
FM DC Notch switchable (DSP W Addr. 0017hex) Mode Tone Control Loudspeaker channel (DSP W Addr. 0020hex H) 5 Band Equalizer (DSP W Addr. 0021hex - 0025hex)
Balance Headphone channel (DSP W Addr. 0030hex H)
1)
This feature will be implemented in MSP 3400C from version C7 on.
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MSP 34x0D
PRELIMINARY DATA SHEET
Feature Audio Baseband Processing
MSP 3400C
MSP 3400D-B4
MSP 3410B-F7
MSP 3410D-B4
Bass for Loudspeaker and Headphone chan. Yes1) (DSP W Addr. 0002/0031hex H) [+20 ...-12 dB] Treble for Loudspeaker and Headphone chan. Yes1) (DSP W Addr. 0003/0032hex H) [+15 ...-12 dB] Loudness Headphone channel (DSP W Addr. 0033hex H) Mode Loudness Headphone channel (DSP W Addr. 0033hex L) SCART1/2 Volume in dB (DSP W Addr. 0007/0040hex H) Scart 2 Volume (DSP W Addr. 0040hex H) Scart 2 Source (DSP W Addr. 0041hex H) Scart 2 Matrix (DSP W Addr. 0041hex L) Yes1) 00hex: normal 04hex: Super Bass1) Yes1) (SCART1) No No No No Yes1)
Yes [+20 ...-12 dB] Yes [+15 ...-12 dB] Yes 00hex: normal 04hex: Super Bass Yes Yes Yes Yes Yes Yes
No No No No
Yes [+20 ...-12 dB] Yes [+15 ...-12 dB] Yes 00hex: normal 04hex: Super Bass Yes Yes Yes Yes Yes Yes
No No No No No No
Full SCART I/O Matrix without restrictions Balance of loudspeaker and headphone channels in dB units (DSP W Addr. 0016/0012hex) Subwoofer output Automatic Volume Correction (AVC)
1)
No No
Yes Yes
No No
Yes Yes
This feature will be implemented in MSP 3400C from version C7 on.
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PRELIMINARY DATA SHEET
MSP 34x0D
9. Specifications 9.1. Outline Dimensions
1.1 x 45 9 1 61 0.48
16 x 1.27 0.1 = 20.32 0.1 1.27 0.1 1.2 x 45
10 2 1.6 9 25.125 0.125
60
0.9
1.27 0.1 15 24.22 0.1
2 0.711
9 0.22 0.07
26 27 25.125 0.125 43
44 1.9 4.05 4.75 0.15
0.1
SPGS7004-3/5E
Fig. 9-1: 68-Pin Plastic Leaded Chip Carrier Package (PLCC68) Weight approximately 4.8 g Dimensions in mm
SPGS0016-4/3E
SPGS0015-1/2E
64
2.5
33
52
27
1
32
3.8 0.1
3
1
26
0.4 0.2 4 0.1
57.7 0.1
(1)
19.3 0.1 18 0.1
0.3 4.8 0.4
47 0.1
15.6 0.1 14 0.1
0.3
3.2 0.4
1.9
0.27 0.06 1.778 0.05
1.29
31 x 1.778 = 55.118 0.1
0.457 1.778 0.05 25 x 1.778 = 44.47 0.1
Fig. 9-2: 64-Pin Plastic Shrink Dual Inline Package (PSDIP64) Weight approximately 9.0 g Dimensions in mm
Fig. 9-3: 52-Pin Plastic Shrink Dual Inline Package (PSDIP52) Weight approximately 5.5 g Dimensions in mm
Micronas
3.2 0.2
0.457
0.24
0.3
1 0.1
20.1 0.5
1 0.1
0.27 0.06 0...15
16 x 1.27 0.1 = 20.32 0.1
23.4
24.22 0.1
55
MSP 34x0D
PRELIMINARY DATA SHEET
23 x 0.8 = 18.4 0.17 0.03 64 65 1.8 17.2 10.3 9.8 16 8 14 41 40 1.8 15 x 0.8 = 12.0 8 0.8 0.8
5 25 1.28 2.70 3 0.2 0.1 20
80 1
24 23.2
SPGS0025-1/1E
Fig. 9-4: 80-Pin Plastic Quad Flat Pack (PQFP80) Weight approximately 1.61 g Dimensions in mm
15 x 0.5 = 7.5 0.5 0.145 48 49 12 33 32 15 x 0.5 = 7.5 0.22 0.5 10
1.75
64 1 1.75 12 16
17
1.4 1.5 0.1
10
D0025/2E
Fig. 9-5: 64-Pin Plastic Low-Profile Quad Flat Pack (PLQFP64) Weight approximately 0.35 g Dimensions in mm
56
Micronas
PRELIMINARY DATA SHEET
MSP 34x0D
9.2. Pin Connections and Short Descriptions NC = not connected (leave vacant for future compatibility reasons) TP = Test Pin (leave vacant; pin is used for production test only) LV = leave vacant X = obligatory; connect as described in application circuit diagram Pin No.
PLCC 68-pin PSDIP 64-pin PSDIP 52-pin PQFP 80-pin PLQFP 64-pin
Pin Name
Type
Connection
(if not used)
Short Description
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
16
14
9
8
ADR_WS NC ADR_DA I2S_DA_IN1 I2S_DA_OUT I2S_WS I2S_CL I2C_DA I2C_CL NC STANDBYQ ADR_SEL D_CTR_OUT0 D_CTR_OUT1 NC NC NC AUD_CL_OUT TP XTAL_OUT XTAL_IN TESTEN ANA_IN2+
OUT
LV LV
ADR word strobe Not connected ADR data output I2S1 data input I2S data output I2S word strobe I2S clock I2C data I2C clock Not connected Standby (low-active) I2C Bus address select Digital control output 0 Digital control output 1 Not connected Not connected Not connected Audio clock output (18.432 MHz) Test pin Crystal oscillator Crystal oscillator Test pin IF input 2
(can be left vacant only if IF input1 is also not in use)
-
15 14 13 12 11 10 9 8 7 6 5 4 3 2
-
13 12 11 10 9 8 7
-
8 7 6 5 4 3 2 1 80 79 78 77 76 75
-
7 6 5 4 3 2 1 64 63 62 61 60 59 58
OUT IN OUT IN/OUT IN/OUT IN/OUT IN/OUT
LV LV LV LV LV X X LV
-
6 5 4 3
IN IN OUT OUT
X X LV LV LV LV LV
- - -
2 1 52 51 50 49
-
1 64 63 62 61 60
-
74 73 72 71 70 69
-
57 56 55 54 53 52
OUT
LV LV
OUT IN IN IN
X X X AVSS via 56 pF / LV AVSS via 56 pF / LV LV
24
59
48
68
51
ANA_IN-
IN
IF common
(can be left vacant only if IF input1 is also not in use)
25
58
47
67
50
ANA_IN1+
IN
IF input 1
Micronas
57
MSP 34x0D
PRELIMINARY DATA SHEET
Pin No.
PLCC 68-pin PSDIP 64-pin PSDIP 52-pin PQFP 80-pin PLQFP 64-pin
Pin Name
Type
Connection
(if not used)
Short Description
26
57
46
66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37
49
AVSUP AVSUP NC NC AVSS AVSS MONO_IN NC VREFTOP SC1_IN_R SC1_IN_L ASG1 SC2_IN_R SC2_IN_L ASG2 SC3_IN_R SC3_IN_L ASG4 SC4_IN_R SC4_IN_L NC AGNDC AHVSS AHVSS NC NC CAPL_M AHVSUP CAPL_A SC1_OUT_L OUT IN IN IN IN IN IN IN IN IN
X X LV LV X X LV LV X LV LV AHVSS LV LV AHVSS LV LV AHVSS LV LV LV or AHVSS X X X LV LV X X X LV
Analog power supply 5V Analog power supply 5V Not connected Not connected Analog ground Analog ground Mono input Not connected Reference voltage IF A/D converter SCART 1 input, right SCART 1 input, left Analog Shield Ground 1 SCART 2 input, right SCART 2 input, left Analog Shield Ground 2 SCART 3 input, right SCART 3 input, left Analog Shield Ground 4 SCART 4 input, right SCART 4 input, left Not connected Analog reference voltage Analog ground Analog ground Not connected Not connected Volume capacitor MAIN Analog power supply 8V Volume capacitor AUX SCART 1 output, left
- - -
27
- - -
56
- - -
45
- - -
48
-
28
-
55
-
44
-
47
-
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
-
54 53 52 51 50 49 48 47 46 45 44 43
-
43 42 41
-
46 45 44 43 42 41 40 39 38 37 36 35
-
40 39
-
38 37
- - - -
36 35
-
42 41
-
34 33
- - -
44 45 46 47
- - -
40 39 38 37
- - -
34 33 32 31
- - -
32 31 30 29
58
Micronas
PRELIMINARY DATA SHEET
MSP 34x0D
Pin No.
PLCC 68-pin PSDIP 64-pin PSDIP 52-pin PQFP 80-pin PLQFP 64-pin
Pin Name
Type
Connection
(if not used)
Short Description
48 49 50 51 52 53 54 55 56 57 58 59 60
36 35 34 33
30 29 28 27
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
28 27 26 25
SC1_OUT_R VREF1 SC2_OUT_L SC2_OUT_R NC NC DACM_SUB NC DACM_L DACM_R VREF2 DACA_L DACA_R NC NC RESETQ NC NC NC I2S_DA_IN2 DVSS DVSS DVSS DVSUP DVSUP DVSUP ADR_CL
OUT
LV X
SCART 1 output, right Reference ground 1 high voltage part SCART 2 output, left SCART 2 output, right Not connected Not connected Subwoofer output Not connected Loudspeaker out, left Loudspeaker out, right Reference ground 2 Headphone out, left Headphone out, right Not connected Not connected Power-on reset Not connected Not connected Not connected I2S2 data input Digital ground Digital ground Digital ground Digital power supply 5V Digital power supply 5V Digital power supply 5V ADR clock
OUT OUT
LV LV LV1) LV LV LV
-
32 31 30 29 28 27 26 25
- -
26
-
24 23 22 21 20 19 18 17
-
25 24 23 22 21
OUT OUT
LV LV X
OUT OUT
LV LV LV LV
- -
61 62 63 64 65 66
- -
24 23 22 21 20 19
- -
20
- -
16 15 14 13 12 11
IN
X LV LV LV
- -
19 18 17
IN
LV X X X X X X
- -
67
- -
18
- -
16
- -
10
- -
68
1)
- -
17
- -
15
- -
9
OUT
LV
Due to compatibility with MSP 3410D-B4 and older versions, it is possible to connect with ground as well.
Micronas
59
MSP 34x0D
9.3. Pin Configurations
PRELIMINARY DATA SHEET
ADR_WS NC ADR_DA I2S_DA_IN1 I2S_DA_OUT I2S_WS I2S_CL I2C_DA I2C_CL ADR_CL DVSUP DVSS I2S_DA_IN2 NC NC NC RESETQ
9 NC STANDBYQ ADR_SEL D_CTR_OUT0 D_CTR_OUT1 NC NC NC AUD_CL_OUT TP XTAL_OUT XTAL_IN TESTEN ANA_IN2+ ANA_IN- ANA_IN1+ AVSUP 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
8
7
6
5
4
3
2
1
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 DACA_R DACA_L VREF2 DACM_R DACM_L NC DACM_SUB NC NC SC2_OUT_R SC2_OUT_L VREF1 SC1_OUT_R SC1_OUT_L CAPL_A AHVSUP CAPL_M
MSP 34x0D
52 51 50 49 48 47 46 45 44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 AVSS MONO_IN VREFTOP SC1_IN_R SC1_IN_L ASG1 SC2_IN_R SC2_IN_L ASG2 NC SC4_IN_L SC4_IN_R ASG4 SC3_IN_L SC3_IN_R AHVSS AGNDC
Fig. 9-6: 68-pin PLCC package
60
Micronas
PRELIMINARY DATA SHEET
MSP 34x0D
AUD_CL_OUT NC NC D_CTR_OUT1 D_CTR_OUT0 ADR_SEL STANDBYQ NC I2C_CL I2C_DA I2S_CL I2S_WS I2S_DA_OUT I2S_DA_IN1 ADR_DA ADR_WS ADR_CL DVSUP DVSS I2S_DA_IN2 NC NC NC RESETQ DACA_R DACA_L VREF2 DACM_R DACM_L NC DACM_SUB NC
1 2 3 4 5 6 7 8 9 10 11 12 13
64 63 62 61 60 59 58 57 56 55 54 53 52
TP XTAL_OUT XTAL_IN TESTEN ANA_IN2+ ANA_IN- ANA_IN+ AVSUP AVSS MONO_IN VREFTOP SC1_IN_R SC1_IN_L ASG1 SC2_IN_R SC2_IN_L ASG2 SC3_IN_R SC3_IN_L ASG4 SC4_IN_R SC4_IN_L AGNDC AHVSS CAPL_M AHVSUP CAPL_A SC1_OUT_L SC1_OUT_R VREF1 SC2_OUT_L SC2_OUT_R
TP AUD_CL_OUT D_CTR_OUT1 D_CTR_OUT0 ADR_SEL STANDBYQ I2C_CL I2C_DA I2S_CL I2S_WS I2S_DA_OUT I2S_DA_IN1 ADR_DA ADR_WS ADR_CL DVSUP DVSS I2S_DA_IN2 NC RESETQ DACA_R DACA_L VREF2 DACM_R DACM_L DACM_SUB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
52 51 50 49 48 47 46 45 44 43
XTAL_OUT XTAL_IN TESTEN ANA_IN2+ ANA_IN- ANA_IN1+ AVSUP AVSS MONO_IN VREFTOP SC1_IN_R SC1_IN_L SC2_IN_R SC2_IN_L SC3_IN_R SC3_IN_L AGNDC AHVSS CAPL_M AHVSUP CAPL_A SC1_OUT_L SC1_OUT_R VREF1 SC2_OUT_L SC2_OUT_R
MSP 34x0D
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
MSP 34x0D
14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
Fig. 9-8: 52-pin PSDIP package
Fig. 9-7: 64-pin PSDIP package
Micronas
61
MSP 34x0D
PRELIMINARY DATA SHEET
SC2_IN_L SC2_IN_R ASG1 SC1_IN_L SC1_IN_R VREFTOP NC MONO_IN AVSS AVSS NC NC
ASG2 SC3_IN_R SC3_IN_L ASG4 SC4_IN_R SC4_IN_L NC AGNDC AHVSS AHVSS NC NC
AVSUP AVSUP ANA_IN1+ ANA_IN- ANA_IN2+ TESTEN XTAL_IN XTAL_OUT TP AUD_CL_OUT NC NC D_CTR_OUT1 D_CTR_OUT0 ADR_SEL STANDBYQ
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 65 40 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 1 2 3 4 5 6 7 8 9 39 38 37 36 35 34
CAPL_M AHVSUP CAPL_A SC1_OUT_L SC1_OUT_R VREF1 SC2_OUT_L SC2_OUT_R ASG3 NC DACM_SUB NC DACM_L DACM_R VREF2 DACA_L
MSP 34x0D
33 32 31 30 29 28 27 26
25 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
NC I2C_CL I2C_DA I2S_CL I2S_WS I2S_DA_OUT I2S_DA_IN1 ADR_DA ADR_WS ADR_CL DVSUP DVSUP NC I2S_DA_IN2 DVSS DVSS DVSS DVSUP NC NC NC RESETQ NC
DACA_R
Fig. 9-9: 80-pin PQFP package
62
Micronas
PRELIMINARY DATA SHEET
MSP 34x0D
SC2_IN_L SC2_IN_R ASG1 SC1_IN_L SC1_IN_R VREFTOP MONO_IN AVSS
ASG2 SC3_IN_R SC3_IN_L ASG4 SC4_IN_R SC4_IN_L AGNDC AHVSS
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 AVSUP ANA_IN1+ ANA_INANA_IN2+ TESTEN XTAL_IN XTAL_OUT TP AUD_CL_OUT NC NC D_CTR_OUT1 D_CTR_OUT0 ADR_SEL STANDBYQ NC 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 I2C_CL I2C_DA I2S_CL I2S_WS I2S_DA_OUT I2S_DA_IN1 ADR_DA ADR_WS NC I2S_DA_IN2 DVSS DVSUP ADR_CL NC NC 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 RESETQ 32 31 30 29 28 27 26 CAPL_M AHVSUP CAPL_A SC1_OUT_L SC1_OUT_R VREF1 SC2_OUT_L SC2_OUT_R NC DACM_SUB NC DACM_L DACM_R VREF2 DACA_L DACA_R
MSP 34x0D
25 24 23 22 21 20 19 18 17
Fig. 9-10: 64-pin PLQFP package
Micronas
63
MSP 34x0D
9.4. Pin Circuits (pin numbers refer to PLCC68 package)
PRELIMINARY DATA SHEET
DVSUP P N GND Fig. 9-11: Output Pins 1, 3, 5, 13, 14, and 68 (ADR_WS, ADR_CL, ADR_DA, I2S_DA_OUT, D_CTR_OUT0/1)
3-30 pF
P
500 k
N
2.5 V
3-30 pF
Fig. 9-15: Output/Input Pins 18, 20, and 21 (AUD_CL_OUT, XTALIN/OUT)
N GND Fig. 9-12: Input/Output Pins 8 and 9 (I2C_DA, I2C_CL) ANAIN1+ ANAIN2+
A D
ANAIN- VREFTOP
Fig. 9-13: Input Pins 4, 11, 12, 61, 62, and 65 (STANDBYQ, ADR_SEL, RESETQ, TESTEN, I2S_DA_IN1, I2S_DA_IN2)
Fig. 9-16: Input Pins 23-25, and 29 (ANA_IN2+, ANA_IN-, ANA_IN1+, VREFTOP)
DVSUP P N GND Fig. 9-14: Input/Output Pins 6 and 7 (I2S_WS, I2S_CL)
24 k
0...2 V
Fig. 9-17: Capacitor Pins 44 and 46 (CAPL_M, CAPL_A)
3.75 V
Fig. 9-18: Input Pin 28 (MONO_IN)
64
Micronas
PRELIMINARY DATA SHEET
MSP 34x0D
40 k
3.75 V
Fig. 9-19: Input Pins 30, 31, 33, 34, 36, 37, 40, and 41 (SC1-4_IN_L/R)
AHVSUP
0...1.2 mA
3.3 k
Fig. 9-20: Output Pins 56, 57, 59, 60, and 54 (DACA_L/R, DACM_L/R, DACM_SUB)
125 k
3.75 V
Fig. 9-21: Pin 42 (AGNDC)
26 pF 120 k
300
3.75 V
Fig. 9-22: Output Pins 47, 48, 50, and 51 (SC_1/2_OUT_L/R)
Micronas
65
MSP 34x0D
9.5. Electrical Characteristics 9.5.1. Absolute Maximum Ratings Symbol TA TS VSUP1 VSUP2 VSUP3 dVSUP23 PTOT Parameter Ambient Operating Temperature Storage Temperature First Supply Voltage Second Supply Voltage Third Supply Voltage Voltage between AVSUP and DVSUP Package Power Dissipation PLCC68 without Heat Spreader PSDIP64 without Heat Spreader PSDIP52 without Heat Spreader PQFP80 without Heat Spreader PLQFP64 without Heat Spreader Input Voltage, all Digital Inputs Input Current, all Digital Pins Input Voltage, all Analog Inputs Input Current, all Analog Inputs Output Current, all SCART Outputs Output Current, all Analog Outputs except SCART Outputs Output Current, other pins connected to capacitors Pin Name Min. 0
PRELIMINARY DATA SHEET
Max. 701) 125 9.0 6.0 6.0 0.5
Unit
- -
AHVSUP DVSUP AVSUP AVSUP, DVSUP
C C
V V V V
-40 -0.3 -0.3 -0.3 -0.5
1200 1300 1200 1000 9601)
mW
VIdig IIdig VIana IIana IOana IOana ICana
1) 2) 3) 4) 5)
-0.3 -
SCn_IN_s,3) MONO_IN SCn_IN_s,3) MONO_IN SCn_OUT_s3) DACp_s3) CAPL_p,3) AGNDC
VSUP2+0.3 +20 VSUP1+0.3 +5
4) 5)
V mA2) V mA2)
-20 -0.3 -5
4) 5)
,
,
4)
4)
4)
4)
PLQFP64: 65 C positive value means current flowing into the circuit "n" means "1", "2", "3", or "4", "s" means "L" or "R", "p" means "M" or "A" The analog outputs are short circuit proof with respect to First Supply Voltage and ground. Total chip power dissipation must not exceed absolute maximum rating.
Stresses beyond those listed in the "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions/Characteristics" of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
66
Micronas
PRELIMINARY DATA SHEET
MSP 34x0D
9.5.2. Recommended Operating Conditions (at TA = 0 to 70 C) Symbol VSUP1 VSUP2 VSUP3 VRLH VRHL Parameter First Supply Voltage Second Supply Voltage Third Supply Voltage RESET Input Low-to-High Transition Voltage RESET Input High-to-Low Transition Voltage (see also Fig. 5-3 on page 20) Digital Input Low Voltage Digital Input High Voltage Digital Input Low Voltage Digital Input High Voltage MSP 34x0D version A1 to B4 MSP 34x0D version C5 and later STANDBYQ Setup Time before Turn-off of Second Supply Voltage STANDBYQ, DVSUP STANDBYQ 0.8 0.5 1 ADR_SEL 0.8 0.2 Pin Name AHVSUP DVSUP AVSUP RESETQ Min. 7.6 4.75 4.75 0.7 0.45 Typ. 8.0 5.0 5.0 Max. 8.7 5.25 5.25 0.8 0.55 Unit V V V DVSUP DVSUP
VDIGIL VDIGIH VDIGIL VDIGIH
0.2
VSUP2 VSUP2 VSUP2 VSUP2 VSUP2
tSTBYQ1
s
I2C-Bus Recommendations VI2CIL VI2CIH tI2C5 tI2C6 tI2C1 tI2C2 tI2C3 tI2C4 fI2C I2C-BUS Input Low Voltage I2C-BUS Input High Voltage I2C-Data Setup Time Before Rising Edge of Clock I2C-Data Hold Time after Falling Edge of Clock I2C START Condition Setup Time I2C STOP Condition Setup Time I2C-Clock Low Pulse Time I2C-Clock High Pulse Time I2C-BUS Frequency I2C_CL I2C_CL, I2C_DA 0.6 55 55 120 120 500 500 1.0 0.3 VSUP2 VSUP2 ns ns ns ns ns ns MHz
Micronas
67
MSP 34x0D
PRELIMINARY DATA SHEET
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
I2S-Bus Recommendations VI2SIH I2S-Data Input High Voltage MSP 34x0D version A1 to B4 MSP 34x0D version C5 and later I2S-Data Input Low Voltage MSP 34x0D version A1 to B4 MSP 34x0D version C5 and later I2S-Data Input Setup Time before Rising Edge of Clock I2S-Data Input Hold Time after Falling Edge of Clock I2S-Clock Input Frequency when MSP in I2S-Slave-Mode I2S-Clock Input Ratio when MSP in I2S-Slave-Mode I2S-Word Strobe Input Frequency when MSP in I2S-Slave-Mode I2S-Input Low Voltage when MSP in I2S-Slave Mode MSP 34x0D version A1 to B4 MSP 34x0D version C5 and later I2S-Input High Voltage when MSP in I2S-Slave Mode MSP 34x0D version A1 to B4 MSP 34x0D version C5 and later I2S-Word Strobe Input Setup Time before Rising Edge of Clock when MSP in I2S-Slave-Mode I2S-Word Strobe Input Hold Time after Falling Edge of Clock when MSP in I2S-Slave-Mode I2S_WS I2S_CL, I2S_WS 0.25 0.2 VSUP2 VSUP2 I2S_CL 0.9 32.0 I2S_DA_IN1/2, I2S_CL I2S_DA_IN1/2 0.25 0.2 0.75 0.5 20 0 1.024 1.1 kHz VSUP2 VSUP2 VSUP2 VSUP2 ns ns MHz
VI2SIL
tI2S1 tI2S2 fI2SCL RI2SCL fI2SWS VI2SIDL
VI2SIDH
0.75 0.5 60
VSUP2 VSUP2 ns
tI2SWS1
tI2SWS2
0
ns
68
Micronas
PRELIMINARY DATA SHEET
MSP 34x0D
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
General Crystal Recommendations fP RR C0 CL Crystal Parallel Resonance Frequency at 12 pF Load Capacitance Crystal Series Resistance Crystal Shunt (Parallel) Capacitance External Load Capacitance1) XTAL_IN, XTAL_OUT PSDIP PLCC P(L)QFP 18.432 8 6.2 1.5 3.3 3.3 25 7.0 MHz
pF pF pF pF
Crystal Recommendations for Master-Slave Applications fTOL DTEM C1 fCL Accuracy of Adjustment Frequency Variation versus Temperature Motional (Dynamic) Capacitance Required Open Loop Clock Frequency (Tamb = 25C) AUD_CL_OUT
-20 -20
19 18.431 24
+20 +20
ppm ppm fF
18.433
MHz
Crystal Recommendations for FM / NICAM Applications (No Master-Slave Mode possible) fTOL DTEM C1 fCL Accuracy of Adjustment Frequency Variation vs. Temp. Motional (Dynamic) Capacitance Required Open Loop Clock Frequency (Tamb = 25 C) AUD_CL_OUT
-30 -30
15
18.4305
+30 +30
ppm ppm fF
18.4335
MHz
Crystal Recommendations for FM Applications (No Master-Slave Mode possible) fTOL DTEM Accuracy of Adjustment Frequency Variation versus Temperature
-100 -50
+100 +50
ppm ppm
Amplitude Recommendation for Operation with External Clock Input (Cload after reset = 22 pF) VXCA
1)
External Clock Amplitude
XTAL_IN
0.7
Vpp
External capacitors at each crystal pin to ground are required. They are necessary to tune the open-loop frequency of the internal PLL and to stabilize the frequency in closed-loop operation. Due to different layouts, the accurate capacitor size should be determined with the customer PCB. The suggested values (1.5...3.3 pF) are figures based on experience and should serve as "start value". To define the capacitor size, reset the MSP without transmitting any further I2C telegrams. Measure the frequency at AUD_CL_OUT-pin. Change the capacitor size until the free running frequency matches 18.432 MHz as closely as possible.The higher the capacity, the lower the resulting clock frequency.
Micronas
69
MSP 34x0D
PRELIMINARY DATA SHEET
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Analog Input and Output Recommendations CAGNDC AGNDC Filter Capacitor Ceramic Capacitor in Parallel CinSC VinSC VinMONO RLSC CLSC CVMA CFMA DC-Decoupling Capacitor in front of SCART Inputs SCART Input Level Input Level, Mono Input SCART Load Resistance SCART Load Capacitance Main/AUX Volume Capacitor Main/AUX Filter Capacitor CAPL_M, CAPL_A DACM_s, DACA_s1) 10 MONO_IN SCn_OUT_s1) 10 6.0 SCn_IN_s1) AGNDC
-20% -20% -20%
3.3 100 330 +20% 2.0 2.0
F
nF nF VRMS VRMS k nF
F
+10% nF
-10%
1
Recommendations for Analog Sound IF Input Signal CVREFTOP VREFTOP Filter Capacitor Ceramic Capacitor in Parallel FIF_FM VIF_FM VIF_AM RFMNI Analog Input Frequency Range Analog Input Range FM/NICAM Analog Input Range AM/NICAM Ratio: NICAM Carrier/FM Carrier (unmodulated carriers) BG: I: Ratio: NICAM Carrier/AM Carrier (unmodulated carriers) Ratio: FM-Main/FM-Sub Satellite Ratio: FM1/FM2 German FM System Ratio: Main FM Carrier/ Color Carrier Ratio: Main FM Carrier/ Luma Components Pass-band Ripple Suppression of Spectrum Above 9.0 MHz Maximum FM Deviation (approx.) normal mode high deviation mode ANA_IN1+, ANA_IN2+, ANA_IN15 15 VREFTOP
-20% -20%
0 0.1 0.1
10 100 9 0.8 0.45 3 0.8 0 0 0
F
nF MHz Vpp Vpp dB dB dB dB dB
-20 -23 -25
-7 -10 -11
7 7
RAMNI RFM RFM1/FM2 RFC RFV PRIF SUPHF FMMAX
- - -
- - 2 -
dB dB dB dB
-
15
192 360
kHz
1)
"n" means "1", "2" or "3", "s" means "L" or "R"
70
Micronas
PRELIMINARY DATA SHEET
MSP 34x0D
9.5.3. Characteristics at TA = 0 to 70 C, fCLOCK = 18.432 MHz, VSUP1 = 7.6 to 8.7 V, VSUP2 = 4.75 to 5.25 V for min./max. values at TA = 60 C, fCLOCK = 18.432 MHz, VSUP1 = 8 V, VSUP2 = 5 V for typical values, TJ = Junction Temperature MAIN (M) = Loudspeaker Channel, AUX (A) = Headphone Channel
Symbol fCLOCK DCLOCK tJITTER VxtalDC tStartup ISUP1A Parameter Clock Input Frequency Clock High to Low Ratio Clock Jitter (verification not provided in production test) DC-Voltage Oscillator Oscillator Start-up Time at VDD Slew-rate of 1 V/1 s First Supply Current (active)
Analog Volume for Main and Aux at 0 dB Analog Volume for Main and Aux at -30 dB
Pin Name XTAL_IN
Min.
Typ. 18.432
Max.
Unit MHz
Test Conditions
45
55 50
% ps
2.5 XTAL_IN, XTAL_OUT AHVSUP 9.6 6.3 3.5 17.1 11.2 5.6 24.6 16.1 7.7 0.4 2
V ms
mA mA mA STANDBYQ = low
ISUP1S ISUP2A
First Supply Current (standby mode) at Tj = 27 C Second Supply Current (active) MSP 34x0D version A1 to B4 MSP 34x0D version C5 and later Third Supply Current (active) MSP 34x0D version A1 to B4 MSP 34x0D version C5 and later Audio Clock Output AC Voltage Audio Clock Output DC Voltage HF Output Resistance Open Circuit Gain AUD_CL_OUT, XTAL_OUT DVSUP
86 50 AVSUP 15 20 AUD_CL_OUT 1.2 0.4
95 70
110 85
mA mA
ISUP3A
25 35 1.8
35 45
mA mA Vpp load = 40 pF Imax = 0.2 mA
VACLKAC VACLKDC routHF_ACL aACL
0.6 140 0.5
VSUP3
Digital Control Outputs VDCTROL VDCTROH I2C-Bus VI2COL II2COH tI2COL1 tI2COL2 I2S-Bus VI2SOL VI2SOH fI2SCL fI2SWS tI2S1/I2S2 I2S-Output Low Voltage I2S-Output High Voltage I2S-Clock Output Frequency I S-Word Strobe Output Frequency I2S-Clock High/Low-Ratio
2
Digital Output Low Voltage Digital Output High Voltage
D_CTR_OUT0, D_CTR_OUT1 4.0
0.4
V V
IDCTR = 1 mA IDCTR = -1 mA
I2C-Data Output Low Voltage I2C-Data Output High Current I C-Data Output Hold Time after Falling Edge of Clock I2C-Data Output Setup Time before Rising Edge of Clock
2
I2C_DA
0.4 1.0
V
II2COL = 3 mA VI2COH = 5 V
A
ns
I2C_DA, I2C_CL
15
100
ns
fI2C = 1 MHz
I2S_WS, I2S_CL, I2S_DA_OUT I2S_CL I2S_WS I2S_CL
0.4 4.0 1024 32.0 0.9 1.0 1.1
V V kHz kHz
II2SOL = 1 mA II2SOH = -1 mA NICAM-PLL closed NICAM-PLL closed
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MSP 34x0D
PRELIMINARY DATA SHEET
Symbol tI2S3 tI2S4 tI2S5 tI2S6
Parameter I2S-Data Setup Time before Rising Edge of Clock I2S-Data Hold Time after Falling Edge of Clock I2S-Word Strobe Setup Time before Rising Edge of Clock I2S-Word Strobe Hold Time after Falling Edge of Clock
Pin Name I2S_CL, I2S_DA_OUT
Min. 200
Typ.
Max.
Unit ns
Test Conditions CL = 30 pF CL = 30 pF CL = 30 pF CL = 30 pF
180
ns
I2S_CL, I2S_WS
200
ns
180
ns
Analog Ground VAGNDC0 AGNDC Open Circuit Voltage MSP 34x0D version A1 to B4 MSP 34x0D version C5 and later AGNDC Output Resistance AGNDC 3.63 3.67 70 3.73 3.77 125 3.83 3.87 180 V V k Rload 10 M
RoutAGN
3 V VAGNDC 4 V
Analog Input Resistance RinSC RinMONO SCART Input Resistance from TA = 0 to 70 C MONO Input Resistance from TA = 0 to 70 C SCn_IN_s1) 25 40 58 k fsignal = 1 kHz, I = 0.05 mA fsignal = 1 kHz, I = 0.1 mA
MONO_IN
15
24
35
k
Audio Analog-to-Digital-Converter VAICL Effective Analog Input Clipping Level for Analog-to-DigitalConversion SCn_IN_s,1) MONO_IN 2.00 2.25 VRMS fsignal = 1 kHz
SCART Outputs RoutSC SCART Output Resistance at Tj = 27 C from TA = 0 to 70 C Deviation of DC-Level at SCART Output from AGNDC Voltage Gain from Analog Input to SCART Output Frequency Response from Analog Input to SCART Output bandwidth: 0 to 20000 Hz Effective Signal Level at SCART-Output during full-scale digital input signal from DSP SCn_IN_s1) MONO_IN SCn_OUT_s1) SCn_OUT_s1) 200 200 330 460 500 +70

mV
fsignal = 1 kHz, I = 0.1 mA
dVOUTSC ASCtoSC frSCtoSC
-70 -1.0 -0.5
+0.5
dB
fsignal = 1 kHz with respect to 1 kHz
+0.5
dB
VoutSC
SCn_OUT_s1)
1.8
1.9
2.0
VRMS
fsignal = 1 kHz
1)
"n" means "1", "2", "3", or "4";
"s" means "L" or "R"
72
Micronas
PRELIMINARY DATA SHEET
MSP 34x0D
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
Main and AUX Outputs RoutMA Main/AUX Output Resistance at Tj = 27 C from TA = 0 to 70 C DC-Level at Main/AUX-Output for Analog Volume at 0 dB for Analog Volume at -30 dB Effective Signal Level at Main/ AUX-Output during full-scale digital input signal from DSP for Analog Volume at 0 dB DACp_s1) 2.1 2.1 3.3 4.6 5.0 k k fsignal = 1 kHz, I = 0.1 mA
VoutDCMA
1.80
2.04 61 1.37
2.28
V mV VRMS fsignal = 1 kHz
VoutMA
1.23
1.51
Analog Performance SNR Signal-to-Noise Ratio from Analog Input to DSP MONO_IN, SCn_IN_s1) 85 88 dB Input Level = -20 dB with resp. to VAICL, fsig= 1 kHz, equally weighted 20 Hz...16 kHz2) Input Level = -20 dB, fsig = 1 kHz, equally weighted 20 Hz...20 kHz Input Level = -20 dB, fsig = 1 kHz, equally weighted 20 Hz...15 kHz3) Input Level = -20 dB, fsig = 1 kHz, equally weighted 20 Hz...15 kHz3)
from Analog Input to SCART Output
MONO_IN, SCn_IN_s1) SCn_OUT_s1) SCn_OUT_s1)
93
96
dB
from DSP to SCART Output
85
88
dB
from DSP to Main/AUX-Output for Analog Volume at 0 dB for Analog Volume at -30 dB
DACp_s1) 85 78 88 83 dB dB
THD
Total Harmonic Distortion from Analog Input to DSP MONO_IN, SCn_IN_s1) 0.01 0.03 % Input Level = -3 dBr with resp. to VAICL, fsig = 1 kHz, equally weighted 20 Hz...16 kHz2) Input Level = -3 dBr, fsig = 1 kHz, equally weighted 20 Hz...20 kHz Input Level = -3 dBr, fsig = 1 kHz, equally weighted 20 Hz...16 kHz3) Input Level = -3 dBr, fsig = 1 kHz, equally weighted 20 Hz...16 kHz3)
from Analog Input to SCART Output
MONO_IN, SCn_IN_s SCn_OUT_s1) SCn_OUT_s1)
0.01
0.03
%
from DSP to SCART Output
0.01
0.03
%
from DSP to Main or AUX Output
DACA_s, DACM_s1)
0.01
0.03
%
1) 2) 3)
"n" means "1", "2", "3", or "4"; DSP measured at I2S-Output DSP Input at I2S-Input
"s" means "L" or "R";
"p" means "M" or "A"
Micronas
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MSP 34x0D
PRELIMINARY DATA SHEET
Symbol XTALK
Parameter Crosstalk attenuation - PLCC68 - PSDIP64
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions Input Level = -3 dB, fsig = 1 kHz, unused analog inputs connected to ground by Z < 1 k equally weighted 20 Hz...20 kHz
between left and right channel within SCART Input/Output pair (LR, RL) SCn_IN SCn_OUT1) SC1_IN or SC2_IN DSP SC3_IN DSP DSP SCn_OUT1) PLCC68 PSDIP64 PLCC68 PSDIP64 PLCC68 PSDIP64 PLCC68 PSDIP64 80 80 80 80 80 80 80 80 dB dB dB dB dB dB dB dB
2)
3)
between left and right channel within Main or AUX Output pair DSP DACp1) between SCART Input/Output pairs1) D = disturbing program O = observed program D: MONO/SCn_IN SCn_OUT O: MONO/SCn_IN SCn_OUT1) D: MONO/SCn_IN SCn_OUT or unsel. O: MONO/SCn_IN DSP1) D: MONO/SCn_IN SCn_OUT O: DSP SCn_OUT1) D: MONO/SCn_IN unselected O: DSP SC1_OUT PLCC68 PSDIP64 PLCC68 PSDIP64 PLCC68 PSDIP64 PLCC68 PSDIP64 100 100 100 95 100 100 100 100 dB dB dB dB dB dB dB dB PLCC68 PSDIP64 80 75 dB dB
equally weighted 20 Hz...16 kHz
3)
(equally weighted 20 Hz...20 kHz same signal source on left and right disturbing channel, effect on each observed output channel
2)
3)
3)
Crosstalk between Main and AUX Output pairs DSP DACp1)
PLCC68 PSDIP64
95 90
dB dB
(equally weighted 20 Hz...16 kHz)3) same signal source on left and right disturbing channel, effect on each observed output channel (equally weighted 20 Hz...20 kHz) same signal source on left and right disturbing channel, effect on each observed output channel
XTALK
Crosstalk from Main or AUX Output to SCART Output and vice-versa D = disturbing program O = observed program D: MONO/SCn_IN/DSP SCn_OUT O: DSP DACp1) D: MONO/SCn_IN/DSP SCn_OUT O: DSP DACp1) D: DSP DACp O: MONO/SCn_IN SCn_OUT1) D: DSP DACM O: DSP SCn_OUT1) PLCC68 PSDIP64 PLCC68 PSDIP64 PLCC68 PSDIP64 PLCC68 PSDIP64 85 80 90 85 100 95 100 95 dB dB dB dB dB dB dB dB
SCART output load resistance 10 k SCART output load resistance 30 k
3)
1) 2) 3)
"n" means "1", "2", "3", or "4"; "p" means "M" or "A" DSP measured at I2S-Output DSP Input at I2S-Input
74
Micronas
PRELIMINARY DATA SHEET
MSP 34x0D
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
PSRR: rejection of noise on AHVSUP at 1 kHz AGNDC From Analog Input to DSP AGNDC MONO_IN, SCn_IN_s1) MONO_IN, SCn_IN_s1), SCn_OUT_s1) SCn_OUT_s1) DACp_s1) DACp_s1), SCn_OUT_s1) DACp_s1), SCn_OUT_s1) 73 80 70 dB dB
From Analog Input to SCART Output
70
dB
From DSP to SCART Output From DSP to MAIN/AUX Output S/NFM THDFM FM Input to Main/AUX/SCART Output Total Harmonic Distortion + Noise of FM demodulated signal on Main/ AUX/SCART output
60 80
dB dB dB 1 FM-carrier 5.5 MHz, 50 s, 1 kHz, 40 kHz deviation; RMS, unweighted 0 to 15 kHz (for S/N); full input range, FM-Prescale = 46h, Vol = 0 dB Output Level 1 VRMS at DACp_s1); SPM = 3 NICAM: -6 dB, 1 kHz, RMS unweighted 0 to 15 kHz, Vol = 9 dB NIC_Presc = 7Fh Output level 1 VRMS at DACp_s1); SPM = 8 2.12 kHz, Modulator input level = 0 dBref SPM = 8 FM+NICAM, norm conditions SIF input range: 0.1-0.8 Vpp; AM = 70 %, 1 kHz, RMS unweighted (S/N); 0 to 15 kHz, FM/AM-Prescale = 3Chex, Vol = 0 dB Output level: 0.5 VRMS at DACp_s1) FM+NICAM, norm conditions; SPM = 9
0.1
%
S/NNICAM
Signal to Noise ratio of NICAM baseband signal on Main/AUX/ SCART outputs
DACp_s1), SCn_OUT_s1)
72
dB
THDNICAM
Total Harmonic Distortion + Noise of NICAM baseband signal on Main/AUX/SCART output NICAM: Bit Error Rate
DACp_s1), SCn_OUT_s1)
0.1
%
BERNI S/NAM
-
DACp_s1), SCn_OUT_s1) DACp_s1), SCn_OUT_s1)
1
10-7
Signal to Noise ratio of AM baseband signal on Main/AUX/SCART outputs Total Harmonic Distortion + Noise of AM demodulated signal on Main/ AUX/SCART output
48
dB
THDAM
0.3
%
1)
"n" means "1", "2", "3", or "4"; "s" means "L" or "R"; SPM: Short Programming Mode
"p" means "Loudspeaker (Main)'' or ``Headphone (AUX)''
Micronas
75
MSP 34x0D
PRELIMINARY DATA SHEET
Symbol RIFIN
Parameter Input Impedance
Pin Name ANA_IN1+, ANA_IN2+, ANA_IN- VREFTOP
Min. 1.5 6.8
Typ. 2 9.1
Max. 2.5 11.4
Unit k k
Test Conditions Gain AGC = 20 dB Gain AGC = 3 dB
DCVREFTOP
DC voltage at VREFTOP MSP 34x0D version A1 to B4 MSP 34x0D version C5 and later DC voltage on IF inputs
2.4 2.56 ANA_IN1+, ANA_IN2+, ANA_IN- ANA_IN1+, ANA_IN2+, ANA_IN- 1.3
2.6 2.66 1.5
2.7 2.76 1.7
V V V
DCANA_IN
XTALKIF BWIF AGC dVFMOUT dVNICAMOUT fRFM
Crosstalk attenuation 3 dB Bandwidth AGC Step Width Tolerance of output voltage of FM demodulated signal Tolerance of output voltage of NICAM baseband signal FM Frequency Response on Main/ AUX/SCART Outputs, Bandwidth 20 to 15000 Hz NICAM Frequency Response on Main/AUX/SCART Outputs, Bandwidth 20 to 15000 Hz FM Channel Separation (Stereo)
40 10 0.85
dB MHz dB +1.5 dB
fsignal = 1 MHz Input Level = -2 dBr
DACp_s1), SCn_OUT_s1) DACp_s1), SCn_OUT_s1) DACp_s1), SCn_OUT_s1) DACp_s1), SCn_OUT_s1) DACp_s1), SCn_OUT_s1)
-1.5 -1.5 -1.0
1 FM-carrier, 50 s, 1 kHz, 40 kHz deviation; RMS 2.12 kHz, Modulator input level = 0 dBref 1 FM-carrier 5.5 MHz, 50 s, Modulator input level = -14.6 dBref; RMS Modulator input level = -12 dB dBref; RMS
+1.5
dB
+1.0
dB
fRNICAM
-1.0
+1.0
dB
SEPFM
50
dB
2 FM-carriers 5.5/5.74 MHz, 50 s, 1 kHz, 40 kHz deviation; RMS
SEPNICAM XTALKFM
NICAM Channel Separation (Stereo) FM Crosstalk Attenuation (Dual)
DACp_s1), SCn_OUT_s1) DACp_s1), SCn_OUT_s1)
80
dB
80
dB
2 FM-carriers 5.5/5.74 MHz, 50 s, 1 kHz, 40 kHz deviation; RMS
XTALKNICAM
1)
NICAM Crosstalk Attenuation (Dual)
DACp_s1), SCn_OUT_s1)
80
dB
"n" means "1", "2", "3", or "4";
"s" means "L" or "R";
"p" means "M" or "A"
76
Micronas
PRELIMINARY DATA SHEET
MSP 34x0D
10. Application Circuit
Tuner 2
IF2 IN
if ANA_IN2+ not used
Signal GND
10 F + 3.3 F 56 pF 56 pF 56 pF + 100 nF 100 nF 18.432 MHz
C see section 9.5.2.
Tuner 1
IF1 IN
+8.0 V
+
+ 10 F 10 F
VREFTOP (54) 29
XTAL_IN (62) 21
AGNDC (42) 42
XTAL_OUT (63) 20
ANA_IN1+ (58) 25
ANA_IN2+ (60) 23
ANA_IN- (59) 24
CAPL_M (40) 44
CAPL_A (38) 46
1 F
330 nF
28 (55) MONO_IN 31 (52) SC1_IN_L 30 (53) SC1_IN_R 32 (51) ASG1
DACM_L (29) 56 1 nF 1 F
330 nF 330 nF AHVSS 330 nF 330 nF AHVSS 330 nF 330 nF AHVSS 330 nF
DACM_R (28) 57 1 nF 1 F DACM_SUB (31) 54 1 nF
Loudspeaker
34 (49) SC2_IN_L 33 (50) SC2_IN_R 35 (48) ASG2 37 (46) SC3_IN_L 36 (47) SC3_IN_R 38 (45) ASG4 40 (43) SC4_IN_L 39 (44) SC4_IN_R DACA_R (25) 60 1 nF DACA_L (26) 59 1 nF 1 F 1 F
Headphones
5V 5V
DVSS DVSS
330 nF
MSP 34x0D
11 (7) STANDBYQ 12 (6) ADR_SEL 8 (10) I2C_DA 9 (9) I2C_CL 1 (16) ADR_WS 68 (17) ADR_CL 3 (15) ADR_DA D_CTR_OUT0 (5) 13 6 (12) I2S_WS 7 (11) I2S_CL 4 (14) I2S_DA_IN1 65 (20) I2S_DA_IN2 5 (13) I2S_DA_OUT 61 (24) RESETQ 45 (39) AHVSUP 67 (18) DVSUP 26 (57) AVSUP 66 (19) DVSS 27 (56) AVSS TESTEN (61) 22 43 (41) AHVSS 49 (35) VREF1 58 (27) VREF2 AUD_CL_OUT (1) 18 D_CTR_OUT1 (4) 14 SC2_OUT_R (33) 51 SC1_OUT_L (37) 47 SC1_OUT_R (36) 48
100 + 100 + 100 SC2_OUT_L (34) 50 + 100 +
22 F 22 F 22 F 22 F
AVSS
100 nF ResetQ (from CCU, see section. 5.3. )
Alternative circuit for ANA_IN1/2+ for more attenuation of video components:
100 p 56 p
*
DVSS
100 nF AVSS
100 nF AHVSS
ANA_IN1/2+
5V 8.0 V
1 k
5V
Micronas
77
MSP 34x0D
PRELIMINARY DATA SHEET
Note: Pin numbers refer to the PLCC68 package; numbers in brackets refer to the PSDIP64 package.
*Application Note: All ground pins should be connected to one low-resistive ground plane. All supply pins should be connected separately with short and low-resistive lines to the power supply. Decoupling capacitors from DVSUP to DVSS, AVSUP to AVSS, and AHVSUP to AHVSS are recommended as closely as possible to these pins. Decoupling of DVSUP and DVSS is most important. We recommend using more than one capacitor. By choosing different values, the frequency range of active decoupling can be extended. In our application boards we use: 220 pF, 470 pF, 1.5 nF, and 10 F. The capacitor with the lowest value should be placed nearest to the DVSUP and DVSS pins. The ASG pins should be connected as closely as possible to the MSP to ground. If they are lead with the SCART input lines as shielding line, they should NOT be connected to ground at the SCART connector.
78
Micronas
PRELIMINARY DATA SHEET
MSP 34x0D
11. Appendix A: MSP 34x0D Version History A1 First hardware release, which is completely compatible to MSP 3410B.
A2 Hardware as A1 with additional features: - Automatic NICAM-FM switching - Demodulator Short Programming - Automatic Standard Detection
B3 Hardware as A2 with additional features: - Automatic Volume Correction (AVC) - Subwoofer Output - improved Automatic Standard Detection - extended Short Programming Mode - automatic reset and selection of identification for Demodulator Short Programming
B4 Hardware and firmware as B3: - Carrier Mute Function not recommended in HighDeviation Mode
C5 - additional package PLQFP64 - digital input specification changed as of version C5 and later (see section 9.5. on page 66) - max. analog high supply voltage AHVSUP 8.7 V - supply currents changed as of version C5 and later (see section 9.5.3. on page 71) - Pin ASG3 no longer supported
Micronas
79
MSP 34x0D
12. Data Sheet History 1. Preliminary data sheet: "MSP 3400D, MSP 3410D Multistandard Sound Processors, Nov. 30, 1998, 6251-482-1PD. First release of the preliminary data sheet. 2. Preliminary data sheet: "MSP 3400D, MSP 3410D Multistandard Sound Processors, May 14, 1999, 6251-482-2PD. Second release of the preliminary data sheet. Major changes: - specification for version C5 added (see Appendix A: Version History) - section 9.: specification for PLQFP64 package added
PRELIMINARY DATA SHEET
Micronas GmbH Hans-Bunte-Strasse 19 D-79108 Freiburg (Germany) P.O. Box 840 D-79008 Freiburg (Germany) Tel. +49-761-517-0 Fax +49-761-517-2174 E-mail: docservice@micronas.com Internet: www.micronas.com Printed in Germany Order No. 6251-482-2PD
All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Any new issue of this data sheet invalidates previous issues. Product availability and delivery are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples delivered. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Further, Micronas GmbH reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. No part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of Micronas GmbH.
80
Micronas
MSP 34xxD
Preliminary Data Sheet Supplement
Subject: Data Sheet Concerned: Supplement: Edition:
Compatibility Differences All MSP 34xxD Data Sheets: 6251-482-2PD, 6251-475-2PD, 6251-486-2PD No. 3/ 6251-526-3PDS Oct. 11, 2000
MSP 34xxD Family Compatibility Differences: The MSP-family (MSP 3410D, MSP 3400D, MSP 3415D, MSP 3405D, MSP 3417D, MSP 3407D) is currently available in different technologies (0.8 , 0.5 , and 0.45 ). The specific differences of the various implementations are listed in the attached table.
Micronas
page 1 of 1
Micronas
Compatibility Differences between 0.5/0.45 and 0.8 MSPD Devices
MSP-Type Version Code Technology Mask Iteration Code Feature
Datasheet Reference
MSP 3410D / MSP 3400D B4 0.8 67, 6B, 6G Documented in
MSP 3400D, MSP 3410D Edit. May 1999
MSP 3415D / MSP 3405D A2 B3 0.5 8D 0.45 G2, G5 H2, H4
MSP 3417D / MSP 3407D A1 0.8 6E, 6F 0.5 8F B2 0.45 G3, G6, H5
C5 0.5 8C and 94 0.45 G1, G4 H1, H3
0.8 6C, 6D
MSP 3405D, MSP 3415D Edit Oct. 1999
MSP 3407D, MSP 3417D Edit Jan. 2000
General Hardware
Power Consumption Total Electromagnetic Radiation (EMR) VAGNDC0 typical DCVREFTOP typical Maximum Vsup1 Digital Input Pin characteristics (I2S_IN1/2, I2S_WS/CL, StANDBYQ) Datasheet Datasheet Datasheet Datasheet Datasheet 910 mW 3.73 V 2.6 V 8.4 V 600 mW less due to less Power Consumption 3.77 V 2.66 V 8.7 V modified specifications (see datasheet) 640 mW 910 mW 3.73 V 2.6 V 8.4 V 600 mW less due to less Power Consumption 3.77 V 2.66 V 8.7 V modified specifications (see datasheet) 640 mW 910 mW 3.73 V 2.6 V 8.4 V 600 mW less due to less Power Consumption 3.77 V 2.66 V 8.7 V modified specifications (see datasheet) 640 mW
Demodulator
Carrier Mute AM-Frequency Response Automatic Standard Detection slightly slower, but more stable: 64ms mute, 500 ms demute more flat faster, more stable and with mutefunction slightly slower, but more stable: 64ms mute, 500 ms demute more flat faster, more stable and with mutefunction slightly slower, but more stable: 64ms mute, 500 ms demute more flat faster, more stable and with mutefunction
Baseband Processing
J17-Deemphasis for FM-Input channels I2S-Bus Frequency response of 50/75s Deemphasis DC_Level (DSP-Reg.: 1Bhex/1Chex ) Datasheet Supplement Datasheet available not available (75s instead of J17) available more flat Level increased by appr. 15% 1*) available not available not available (75s instead of J17) available more flat Level increased by appr. 15% 1*) available not available (75s instead of J17) not available more flat Level increased by appr. 15% 1*)
Date: 11.10.00
Page 1 of 2 Pages
Micronas
MSP-Type Version Code Technology Mask Iteration Code Feature D/A-Outputs
S/N-ratio -
MSP 3410D / MSP 3400D B4 0.8 67, 6B, 6G Documented in 0.5 8C and 94 C5 0.45 G1, G4 H1, H3
MSP 3415D / MSP 3405D A2 0.8 6C, 6D 0.5 8D B3 0.45 G2, G5 H2, H4
MSP 3417D / MSP 3407D A1 0.8 6E, 6F 0.5 8F B2 0.45 G3, G6, H5
improved
-
improved
-
improved
Pinning
SCART2_Out pin DAC-Headphone pins Audio_Clock_Out The following pins refer to PQFP80: Pin 52 Pin 32 Pin 14 Pin 16 Datasheet Datasheet Datasheet Datasheet ASG2 ASG3 not connected DVSS ASG2 ASG2 ASG2 ASG3 not connected DVSS not connected (s. Datasheet P.51) not connected (s. Datasheet P.51) DVSS not connected DVSS not connected MSP 34x7D not available in 80-PQFP MSP 34x7D not available in 80-PQFP MSP 34x7D not available in 80-PQFP MSP 34x7D not available in 80-PQFP Datasheet Datasheet Datasheet connected connected connected connected not connected not connected not connected (s. Datasheet P.51) connected connected not connected not connected not connected
not connected (s. Datasheet P.59) DVSS not connected DVSS not connected
*1) In spite of increased DC-level controller-algorithms for automatic Sat-Carrier detection should run properly
Date: 11.10.00
Page 2 of 2 Pages

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